Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
19845 Discussions

Receiver Skew Margin for LVDS Mode

Jens
Novice
218 Views

Hi,

for calculation of RSKM (Cyclone 5 handbook, CV-52005 2020.07.24) one need a SW value:

SW—the period of time that the input data must be stable to ensure that data is successfully sampled by
the LVDS receiver. The SW is a device property and varies with device speed grade

 

Does anybody know where to find that value?

 

Jens

0 Kudos
4 Replies
sstrell
Honored Contributor III
206 Views

When you run the RSKM report in the timing analyzer, it reports the sampling window for the targeted device.

Jens
Novice
184 Views

Thank you. For running that report I need a design. I wanted to make an assessment beforehand.

 

Jens

Ash_R_Intel
Employee
171 Views

Hi,

Sampling Window specification is provided in the datasheet. Refer: https://www.intel.com/content/www/us/en/docs/programmable/683801/current/high-speed-i-o-specifications.html


Regards


Jens
Novice
164 Views

Hi,

thank you, that's what I was looking for.

 

Regards

Jens

Reply