Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Receiver Skew Margin for LVDS Mode

Jens
Novice
642 Views

Hi,

for calculation of RSKM (Cyclone 5 handbook, CV-52005 2020.07.24) one need a SW value:

SW—the period of time that the input data must be stable to ensure that data is successfully sampled by
the LVDS receiver. The SW is a device property and varies with device speed grade

 

Does anybody know where to find that value?

 

Jens

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sstrell
Honored Contributor III
630 Views

When you run the RSKM report in the timing analyzer, it reports the sampling window for the targeted device.

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Jens
Novice
608 Views

Thank you. For running that report I need a design. I wanted to make an assessment beforehand.

 

Jens

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Ash_R_Intel
Employee
595 Views

Hi,

Sampling Window specification is provided in the datasheet. Refer: https://www.intel.com/content/www/us/en/docs/programmable/683801/current/high-speed-i-o-specifications.html


Regards


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Jens
Novice
588 Views

Hi,

thank you, that's what I was looking for.

 

Regards

Jens

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