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Valued Contributor III
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Receiver to FPGA

Hi, 

My project goal is to connect a receiver of 15Mbps to computer through FPGA DE3/DE4. 

I want to ask which component should i connect my receiver? and if i need clk from the receiver as well? 

 

Tnx 

Tzahi
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Valued Contributor III
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Re: Receiver to FPGA

How does the 15Mbps data arrive to you? (Ethernet? parallel bus? high-speed transceiver? other?) I would suggest you send your data over Ethernet to the computer unless there is a compelling reason not to.

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Valued Contributor III
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Re: Receiver to FPGA

 

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How does the 15Mbps data arrive to you? (Ethernet? parallel bus? high-speed transceiver? other?) I would suggest you send your data over Ethernet to the computer unless there is a compelling reason not to. 

--- Quote End ---  

 

 

 

The data arrives by high speed serial receiver - image attached. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=6574  

Tnx, 

Tzahi
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Valued Contributor III
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Re: Receiver to FPGA

Serial data transmission depends on protocols. You have to select a suitable protocol than can be decoded at the FPGA side. Stratix III and IV FPGA offer a soft CDR feature with fast serial receiver channels that can be helpful to decode synchronous data streams. Using asynchronous (UART) protocols would be another option. 

 

The output of the Linear demo circuit is apparently an amplified analog photo diode signal. It has to be converted to a digital data stream by a suitable circuit, e.g. a comparator. It might be possible to "abuse" a Stratix LVDS receiver as comparator, but the output voltage of the TIA must be limited to a safe FPGA input range before.
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Valued Contributor III
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Re: Receiver to FPGA

 

--- Quote Start ---  

Serial data transmission depends on protocols. You have to select a suitable protocol than can be decoded at the FPGA side. Stratix III and IV FPGA offer a soft CDR feature with fast serial receiver channels that can be helpful to decode synchronous data streams. Using asynchronous (UART) protocols would be another option. 

 

The output of the Linear demo circuit is apparently an amplified analog photo diode signal. It has to be converted to a digital data stream by a suitable circuit, e.g. a comparator. It might be possible to "abuse" a Stratix LVDS receiver as comparator, but the output voltage of the TIA must be limited to a safe FPGA input range before. 

--- Quote End ---  

 

 

 

I already have a comparator in my circuit (look at the image attached above) and i can't use synchronous data stream because my circuit has no clock. 

I want to know how can i connect my circuit (Linear demo circuit followed by comparator) to any FPGA that will ensure me data rates of 15Mbps. 

 

Tanks a lot. 

Tzahi
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Valued Contributor III
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Re: Receiver to FPGA

 

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I already have a comparator in my circuit (look at the image attached above) 

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I have seen the image and noticed that the comparator isn't connected to the TIA output signal. Thus I don't recognize a relation to your question. 

 

 

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i can't use synchronous data stream because my circuit has no clock 

--- Quote End ---  

 

I don't agree. As said, Stratix can use soft CDR to extract the clock.
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Valued Contributor III
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Re: Receiver to FPGA

 

--- Quote Start ---  

As said, Stratix can use soft CDR to extract the clock. 

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At 15 Mbps you can also use a DPLL (running at 8x or 16x the bitrate) and get away with Cyclone devices (-6 speed grade perhaps for the x16 case)
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Valued Contributor III
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Re: Receiver to FPGA

 

--- Quote Start ---  

At 15 Mbps you can also use a DPLL (running at 8x or 16x the bitrate) and get away with Cyclone devices (-6 speed grade perhaps for the x16 case) 

--- Quote End ---  

 

 

Right. With Cylone III and above, you can also implement a kind of soft CDR based on PLL dynamic phase shift capability, working at considerably higher data rates. I didn't mention Cyclone related solutions, because tzahi is explicitely asking for DE3/DE4 (Stratix based) dev kits.
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