Reduce clock frequency when system clock is dynamic

[Altera_Forum]

Hi, I would like to know a method to divide the clock to a certain frequency. I am aware of different methods of clock divider but the thing here is that the on-board system clock is dynamic (not fixed to a constant frequency) and I want to have a constant 10 Hz when running.  

The CPLD I am using currently is 5m160ze64.  Any idea?  Thanks!

[Altera_Forum]

What is the min/max range of the dynamic clock? What is the rate of change of the dynamic clock? 

 The simple solution of course would be to just add a fixed 50MHz (or whatever) crystal oscillator part to provide a constant reference into your FPGA, and divide it down to 10Hz (or whatever).  Without having some sort of fixed reference it is impossible to know how much to divide a dynamic clock by to achieve a constant 10Hz output.  You seem to be looking for a very complex solution to a problem that is much easier to solve using a more standard approach (a fixed frequency source).

[Altera_Forum]

Actually I am not sure what the min/max range of the dynamic clock is. If I can config the on-board clock to be fixed frequency I can of course do that, but I am not sure how. Do I need to create a Synopsis Design Constraint (SDC) file and then calculate the frequency or is there another way to obtain fixed frequency on the on-board clock? 

 Thanks.

[Altera_Forum]

--- Quote Start ---  Actually I am not sure what the min/max range of the dynamic clock is.  --- Quote End ---    Well, until you know that for certain using that dynamic clock for a reference, or anything else, is nigh impossible.    --- Quote Start ---  If I can config the on-board clock to be fixed frequency I can of course do that, but I am not sure how. Do I need to create a Synopsis Design Constraint (SDC) file and then calculate the frequency or is there another way to obtain fixed frequency on the on-board clock?  Thanks.  --- Quote End ---    Well, any 'on board clock' (if present) should have its parameters listed in a user manual and/or schematic. It would usually be a fixed frequency crystal oscillator attached to a specific FPGA pin. You have to look at your board, read the user manual, or read the schematic (I assume you have access to the latter two items?)  You could then use that frequency to help define your SDC contraints for layout and timing analysis.  update: Itappears the 5m160ze64 part you are using has an internal oscillator in the UFM block with an output that can range from 3.9 to 5.3 MHz. The exact frequency is not programmable, it will vary from device to device, and over temperature and voltage. So it could conceivably be used as an (internal) reference, assuming you can live with the frequency variation.

[Altera_Forum]

--- Quote Start ---   update: Itappears the 5m160ze64 part you are using has an internal oscillator in the UFM block with an output that can range from 3.9 to 5.3 MHz. The exact frequency is not programmable, it will vary from device to device, and over temperature and voltage. So it could conceivably be used as an (internal) reference, assuming you can live with the frequency variation.  --- Quote End ---    Thanks! Could you give a reference about frequency variation of the UFM oscillator, so I can read more about it? I found the details about 3.9-5.3 MHz, but not about not being programmable and the frequency variations. Also is the internal oscillator in the UFM block the only oscillator option for 5m160ze64 or does it consist of another on-board oscillator?

[Altera_Forum]

--- Quote Start ---  Thanks! Could you give a reference about frequency variation of the UFM oscillator, so I can read more about it? I found the details about 3.9-5.3 MHz, but not about not being programmable and the frequency variations. Also is the internal oscillator in the UFM block the only oscillator option for 5m160ze64 or does it consist of another on-board oscillator?  --- Quote End ---    The internal UFM oscillator block is NOT programmable in frequency. The spec is that it may be anywhere between 3.9 and 5.3 MHz on a device, so you get what you get, and have to accept that variability. The Altera/Intel MaxV device datasheet has all the details about the internal oscillator specs and usage.  The UFM oscillator is the ONLY internal oscillator for that device. Any other 'on board' oscillator would have to be provided/designed into the BOARD your CPLD device is located on. You don't say where you are using a standard development board, or if this is a custom board design done by you or someone else. So it is up to your board/system designer to provide any other clock reference into your part.

[Altera_Forum]

--- Quote Start ---  The internal UFM oscillator block is NOT programmable in frequency. The spec is that it may be anywhere between 3.9 and 5.3 MHz on a device, so you get what you get, and have to accept that variability. The Altera/Intel MaxV device datasheet has all the details about the internal oscillator specs and usage.  So, if I understand it correctly I can not guess/calculate the accurate frequency of the internal clock? I have read that I can calculate the relative frequency the CPLD will run on and take that as an accurate constant clock. Can that be true?

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---  The internal UFM oscillator block is NOT programmable in frequency. The spec is that it may be anywhere between 3.9 and 5.3 MHz on a device, so you get what you get, and have to accept that variability. The Altera/Intel MaxV device datasheet has all the details about the internal oscillator specs and usage.  --- Quote End ---    So, if I understand it correctly I can not guess/calculate the accurate frequency of the internal clock? I have read that I can calculate the relative frequency the CPLD will run on and take that as an accurate constant clock. Can that be true?  --- Quote End ---    'Guess/calculate the accurate frequency of the internal clock?' ... You can assume, as I said before, the internal clock will be between 3.9 and 5.3MHz. Or as 4.6MHz +/- 0.7MHz. So I suppose you could 'guess' 4.6MHz, but it has a +/- 700KHz uncertainty.  'I have read that I can calculate the relative frequency the CPLD will run on and take that as an accurate constant clock. ' ... I am not sure what you mean by 'relative frequency'? Relative to what? As far as 'accuracy' goes, read my previous answer. Accuracy is +/- 15%. If you want 'normal' accuracy, like of a crystal oscillator, it would be measured in parts per million. Something like 20ppm to 100ppm would be typical.

[Altera_Forum]

--- Quote Start ---  'Guess/calculate the accurate frequency of the internal clock?' ... You can assume, as I said before, the internal clock will be between 3.9 and 5.3MHz. Or as 4.6MHz +/- 0.7MHz. So I suppose you could 'guess' 4.6MHz, but it has a +/- 700KHz uncertainty.  I see. Thanks for the clarification. Last question: Is it only necessary to create SDC files if I want to analyze the timing or do I need to create it each time in order to generate the bin file?

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---  'Guess/calculate the accurate frequency of the internal clock?' ... You can assume, as I said before, the internal clock will be between 3.9 and 5.3MHz. Or as 4.6MHz +/- 0.7MHz. So I suppose you could 'guess' 4.6MHz, but it has a +/- 700KHz uncertainty.  I see. Thanks for the clarification. Last question: Is it only necessary to create SDC files if I want to analyze the timing or do I need to create it each time in order to generate the bin file?  --- Quote End ---    The .sdc files are not just for timing analysis. They also provide info to the fitter in driving the place and route. So the more guidance you can provide to the tool, the better design you will get.