Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21269 Discussions

Remote Clock Pin feeding PLL - Cyclone III

UMall1
New Contributor I
702 Views

I am using a Cyclone III Device for a project. I need 2 Serdes and 2 other PLL for my instrument. I receive the following warning for 1 of my PLL and 1 of my Serdes: 

 

Critical Warning (176598): PLL "CIRCULAR_BUFFER_WITH_DPA:U_CIRCULAR_BUFFER|SERDES:U_SENSOR_1|SERDES_PLL:U_PLL|altpll:altpll_component|SERDES_PLL_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T21" 

 

I have placed this pin in other locations and they produce the same Critical Warning. Where can I find a list of pins that are not remote pins for the PLL in a cyclone III - EP3C80F484C6 - device.

0 Kudos
1 Solution
UMall1
New Contributor I
687 Views

This matter has been resolved.

View solution in original post

0 Kudos
2 Replies
UMall1
New Contributor I
688 Views

This matter has been resolved.

0 Kudos
AqidAyman_Intel
Employee
636 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


0 Kudos
Reply