Remote Configuration scheme

Altera_Forum · ‎04-26-2014

Hi Guys,

I am using the following configuration scheme, want your suggestions and opinions on the same.

(configuration image attached)

1. The Master FPGA boots itself from Serial Configuration Device using Active Serial Configuration receiving configuration data over serial interface.

2. USB, Ethernet and UART Controllers are instantiated in Master FPGA through which configuration data (of slave fpgas) is received and sent to the slave FPGAs (incase of reconfiguration) through Serial Transceiver directly or indirectly through CFI Flash.

3. When the Slave FPGA is first powered up in remote mode, it loads the factory configuration image located at page zero which corresponds to the start address 0x000000 in serial configuration device (EPCS).

4. The factory configuration image writes the remote system upgrade control register to specify the address of the application configuration to be loaded.

5. When the FPGA successfully loads the application configuration, it enters user mode. In user mode, the soft logic (the Nios II processor or state machine and the remote communication interface) assists in determining when a remote system update (through serial transceiver) is arriving. When a remote system update arrives, the soft logic receives the incoming data, writes it to the configuration memory device and triggers the device to load the factory configuration.

6. The factory configuration reads the remote system upgrade status register, determines the valid application configuration to load, writes the remote system upgrade control register accordingly, and starts.

Thanks.

Altera_Forum · ‎04-28-2014

It all sounds very exciting. After all that, does it do anything?

Altera_Forum · ‎04-28-2014

Basically, I want to reconfigure the slave FPGAs through Ethernet, USB and UART which are interfaced with the Master Controller.

Also, slave FPGAs being interfaced with the master in 19 inch backplane, using serial transceiver seems an ideal choice (as their would be latching problem in parallel data bus)