Removing signaltap causes logic to work

[Altera_Forum]

Hi All, 

 I am seeing something strange. I have a design with signaltap instantiated. It compiles without any timing errors. But it does not behave correctly in the hardware. Actually, there are multiple instances of the design in the hardware and only one instance doesn't work.   What's strange is that removing signaltap gets the design to work.  The general design area where I see the problem is here -  ip-hdr registers --> chksum logic cone --> ip hdr chksum registers  Both the source and destination registers are clocked using the same clock and I get no timing errors on these. The timing with or without signal tap passes at all the corners. I have multicorner settings turned on in Quartus.  The above logic is in a module that is replicated in the design using a generate block. On the network analyzer, I see that only one particular instance of the module has a problem. All the header bits are correct except for the checksum field. There are a couple of bits in the checksum field that are always stuck at "1". Rest of the checksum bits also add up. I am using systemverilog interfaces in the module.  I am just curious at this point if someone has also experienced similar issues when working with signal tap.  -sanjay

[Altera_Forum]

Note that SignalTap shouldn't be any different than adding other HDL that brings nodes to a RAM. It shouldn't affect your design. 

That being said, if you add SignalTap and compile from scratch, that is like running another seed and hence a different place and route. So my guess is that you have a timing issue and SignalTap causes a different place-and-route that causes the problem. (By timing error, I mean a path that isn't being analyzed properly, as it is meeting timing.) Luckily, the one that fails has signaltap in it. Make a copy of the design(just being careful to preserve failing design), then go to Assignments -> Partitions Window. Set the partitions in your design(most likely it's just the default Top) to post-fit. This will lock down the placement and routing. Then open SignalTap and change the probe points to get closer to where your failing. Compile.  This will keep your design locked down, and it should continue to fail, while SignalTap can get you to monitor where the failure is occuring. It will probably take multiple iterations of changing the probe points. Good luck.

[Altera_Forum]

Yeah! That is what confuses me. But I like your idea of preserving the partition and then moving the probe points. 

 Thx. Sanjay

[Altera_Forum]

--- Quote Start ---  go to Assignments -> Partitions Window. Set the partitions in your design(most likely it's just the default Top) to post-fit. This will lock down the placement and routing.  --- Quote End ---     If u add changes to the VHDL code, what will happen with the design if this is enabled?