Resuming execution in HPS after FPGA execution

[Altera_Forum]

Hello everyone! I am new with the Cyclone V and I am trying to resume execution in HPS after FPGA execution. 

 I have a HW block developed that will be in the FPGA. From the HPS, this block will receive some data, the block will process it and once the execution is done, I want the FPGA indicates it to the HPS, and so the HPS resume its execution. I have read some about the possibility of used SEV and WFE/WFI ARMv7 instructions, but I don't get how to use it in implementation.  I really appreciate any insight about how to manage this in the best way possible.  Thanks in advance!

[Altera_Forum]

--- Quote Start ---  Hello everyone! I am new with the Cyclone V and I am trying to resume execution in HPS after FPGA execution.  I have a HW block developed that will be in the FPGA. From the HPS, this block will receive some data, the block will process it and once the execution is done, I want the FPGA indicates it to the HPS, and so the HPS resume its execution. I have read some about the possibility of used SEV and WFE/WFI ARMv7 instructions, but I don't get how to use it in implementation.  I really appreciate any insight about how to manage this in the best way possible.  Thanks in advance!  --- Quote End ---    This depends on a couple things. If you're willing to write a kernel module (best option), then you just connect an interrupt line from your block back to the HPS and use the interrupt line to signal that the execution is done. Another possibility is to connect the block to the FPGA-to-HPS line and push directly in to RAM or send instructions directly elsewhere. WFI or WFE will tell the processor to wait for an interrupt, but I'd do it in OS context as this will basically halt a processor. If you're running in bare metal, then you can do such things, but understand the risks. Recently, we've just been using a GPIO interrupt in to a PIO for simplicity, using a poll or select to watch for the line. It adds latency, but doesn't require us to write any kernel modules. Definitely only good for development, though.

[Altera_Forum]

Hi Derim, 

 thanks for your answer. I will trying with this kernel module option. The idea is to make it in the most power efficient way, but if this solve the problem by now, then I can try to improve the solution.  Thanks again!    --- Quote Start ---  This depends on a couple things. If you're willing to write a kernel module (best option), then you just connect an interrupt line from your block back to the HPS and use the interrupt line to signal that the execution is done. Another possibility is to connect the block to the FPGA-to-HPS line and push directly in to RAM or send instructions directly elsewhere. WFI or WFE will tell the processor to wait for an interrupt, but I'd do it in OS context as this will basically halt a processor. If you're running in bare metal, then you can do such things, but understand the risks. Recently, we've just been using a GPIO interrupt in to a PIO for simplicity, using a poll or select to watch for the line. It adds latency, but doesn't require us to write any kernel modules. Definitely only good for development, though.  --- Quote End ---