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Rise time & fall time specs of Stratix II I/Os

Altera_Forum
Honored Contributor II
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Hi, 

 

Is there any rise time & fall time of general I/Os specs? I can't find it in Stratix II data sheets. Will capacitors connect to VCC of FPGA affect the rise & fall time timing? How is the calculation done? Anyway to control the timing? 

 

Can anyone advise? Really appreaciate it.
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