Risk of one pin of 3.0 VCCIO bank connect to 5V logic?

[GWang31]

Hello,

I wrongly connect an I/O pin which is in 3.0V bank to 5V logic. I wonder will the damage(if happens) only affect to this specific pin or the whole FPGA? Will it help if I set this pin to high-z state? The function of this pin is not in need in my design at present, I wonder if there is risk for my rest of FPGA pins. Thanks.

[AnandRaj_S_Intel]

Hi,

Check your device Data Sheet for Absolute Maximum Ratings.

• If we Operate a device in Absolute Maximum Ratings may cause permanent damage to the device.
• The device output pins do not meet the I/O standard specifications if the VCCIO level is out of the recommended operating range for the I/O standard.
• If high-z may impact on  power-on-reset.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand

[GWang31]

Thanks Anand. The maxinum ratings on datasheet of cyclone IV is 4.2V, now the IO pin I connect to 5V logic output by mistake. I know there may be damage to the device. I wonder what the "damage to the device" means. Does it mean the damage to the pin or the whole FPGA? Will the FPGA die?

[AnandRaj_S_Intel]

​Hi,

Yes, If a power supply pin is damaged due to over supply than it may establish a short between VCCIO and GND which means FPGA is damaged. So FPGA will not work.

Regards

Anand

[GWang31]

Hi Anand,

This wrong connected pin is not power supply pin, will that make the FPGA don't work?

[AnandRaj_S_Intel]

​Hi,

VCCIO PIN is connected to 5V right?

if so FPGA will be damaged.

if it's unused IO pin it should be connected to vccio or gnd. If you have pulled IO pin to 5volt we are operating device in maximum rating it will also damage the device.

we cannot guarantee reliability /performance if you are operating device in absolute maximum rating.

[GWang31]

Hi Anand,

Thanks.

VCCIO PIN is connected to 3V. Only one I/O pin in this 3.0V bank is connected to 5V. I measure the voltage on this pin, and it is clamped to 3.8V. Will that damage the FPGA or this I/O pin of FPGA?

[AnandRaj_S_Intel]

​Hi,

We can check the data sheet for DC input voltage.

5 volt is above Absolute Maximum Ratings. It will damage IO pin which may establish a VCCIO and GND short leads to FPGA damage.

Regards

Anand

[Daixiwen]

Is there a resistor limiting the current on that pin? Internally the FPGA has a clamping diode (if you didn't disable it) between the I/O pin and the VCCIO rail of that bank. If the diode is damaged due to the current, then the overvoltage could be transmitted to the VCCIO rail and this would damage more than just the I/O pin on the FPGA.