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Honored Contributor I
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Routing USB through FPGA

Hi, 

 

I'm having some difficulties routing USB through my DE-1 FPGA board. The goal is to make the FPGA chip look like a bare wire to an USB throughput. The thought was to have it perform the handshake and interfere with the throughgoing signal. 

 

But i'm not having any luck with the ALTIO buff prim, because there is too little documentation to have it going the right way. And I was wondering if it's the right way to go about the problem?
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Honored Contributor I
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Assuming I understand you correctly, I don't think this is at all practical. 

 

Are you proposing to intercept the USB line (D+/D-)? Are you proposing to interpret the data on the line and determine when to turn the bus around? 

 

Does Cyclone II (or Cyclone V, depending on DE-1 board) support the USB I/O standard or an alternative, suitable I/O standard? Which I/O standard are you proposing to use? 

 

I think, without dedicated USB phys attached to the FPGA, you're not likely to get anywhere. 

 

Take a look at ftdi (http://www.ftdichip.com/). They do plenty of USB phys which you could attach to an FPGA. You may be able to do what you're trying to do by connecting two to your FPGA 'back-to-back', so to speak. 

 

Cheers, 

Alex
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Honored Contributor I
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No, Im just new to LVDS signals and wanted to route the complete differential signal into my FPGA chip and out again. Having some minimal routine (clock -> buffer) pass along the entire signal. As tho it where a piece of wire. 

I have a cyclone 5 so it has the 2.5V LVDS. And a nice fractional crystal oscillator @72Mhz. 

 

But if I understand correctly, the thing you are suggesting is that my design needs bidirectional differential signals in order to work? Or minimally to spoof some outgoing signal to a computer? 

 

I will take a look at FTDI phy chips, but the spoofing part is important. And want to consider part1 first. 

 

Regards, 

Lukas.
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Honored Contributor I
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What you are trying to do is not practical using a simple FPGA differential receiver / transmitter. Per USB docs: 

 

 

--- Quote Start ---  

USB uses a differential transmission pair for data. This is encoded using NRZI and is bit stuffed to ensure adequate transitions in the data stream. On low and full speed devices, a differential ‘1’ is transmitted by pulling D+ over 2.8V with a 15K ohm resistor pulled to ground and D- under 0.3V with a 1.5K ohm resistor pulled to 3.6V. A differential ‘0’ on the other hand is a D- greater than 2.8V and a D+ less than 0.3V with the same appropriate pull down/up resistors. 

 

The receiver defines a differential ‘1’ as D+ 200mV greater than D- and a differential ‘0’ as D+ 200mV less than D-. The polarity of the signal is inverted depending on the speed of the bus. Therefore the terms ‘J’ and ‘K’ states are used in signifying the logic levels. In low speed a ‘J’ state is a differential 0. In high speed a ‘J’ state is a differential 1. 

 

usb transceivers will have both differential and single ended outputs. certain bus states are indicated by single ended signals on d+, d- or both. for example a single ended zero or se0 can be used to signify a device reset if held for more than 10ms. a se0 is generated by holding both d- and d+ low (< 0.3v). single ended and differential outputs are important to note if you are using a transceiver and fpga as your usb device. you cannot get away with sampling just the differential output.  

--- Quote End ---  

 

 

So your best bet is really to use a separate USB PHY device that understands the USB protocol at the hardware level.
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Honored Contributor I
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Ah I was hoping this would be a sparkling example of a bidirectional ALTIOBUF in action.  

The suggestion is to make "this" then.https://alteraforum.com/forum/attachment.php?attachmentid=13590&stc=1  

 

I'm wondering tho if this is not harder to make, since it requires a tonne of setting up with no guarantee it is actually designed to intercept a USB signal in the way it's intended. Having to set up a mode register to create a device from scratch. I was looking at http://www.ti.com/lit/ds/symlink/tusb1310.pdf . Is there a goto part for this? 

 

 

Also I'm veering in other directions still, since the signal can be transmitted by the simplest wire. So I can always bare wire the handshake. and spoof over with a signal. Still looking if my FPGA can generate such voltages, since I may need a higher voltage standard. So, I'm thinking reading the spec, isn't this just 5v TTL, it seems very close, close enough? 

 

 

--- Quote Start ---  

A differential ‘1’ is transmitted by pulling D+ over 2.8V with a 15K ohm resistor pulled to ground and D- under 0.3V with a 1.5K ohm resistor 

--- Quote End ---  

 

 

Regards, 

Lukas.
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Honored Contributor I
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So I made this.. And tied the terminals together at board level to combine them into bidirectional signals. But it's not working i'm wondering if either the code is wrong or..? Maybe somebody can help me out with this? 

 

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Honored Contributor I
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Well, tests like this: 

 

if (InForw > 1'bZ)  

 

make absolutely no sense, either in pure simulation or especially in compiled FPGA logic. 

 

Your input value (single ended) will be either 1'b0 or 1'b1. It will never be 1'bZ (or 1'bX) in the real world. 

 

You need to reconsider what you are trying to do.
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Honored Contributor I
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Ok, Found it to be a shortcut. These GPIO headers are a bit underpowerd at 3.3v also. 

"I will edit the posted code some" Thx for the fast response, it has been very helpfull!
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Honored Contributor I
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USB is 3.3V not 5V TTL. It's also not LVDS as has been pointed out. 

 

It's a bidirectional bus using two data lines which are sometimes bit not always in anti-phase (differential). On top of that the slave device needs to be able to signal to the host device using a specific pull-up/pull-down resistor values which cannot be emulated directly with the FPGA. 

 

You also have to know exactly when to change the direction of the data bus - if you are driving onto the data lines and don't switch to tristate before the device at the other starts driving onto the data lines you will end up with bus contention which will not do anything any good. 

 

The FPGA I/O pins are not designed for hosting USB interfaces. You would need a separate PHY. 

 

USB is not designed to have devices placed in the middle of the bus unless they are specifically configured as USB Hubs. A hub is very different from a simple pass through. They are separate USB devices. The host talks to the hub directly, and asks it nicely to relay messages to other devices connected to the hub.
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Novice
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Hello,

 

This may be a bit off track but this may be useful to someone in future.

 

Here are the reasons why we need an external PHY chip.

 

(1) USB requires both differential and single ended signalling. Certain bus states are indicated by single ended signals. For example, single ended zero (SE0) is used to perform USB reset operation. It is generated by holding both D+ and D- lines at low. During data transfer, it uses differential signaling. In order to get more idea, you are requested to refer section 7.1 Signalling from USB2.0 Specification.

It shows high-speed capable transceiver circuit.

 

(2) It also uses some pull-up or pull-down registers. Either some pull-up registers or termination registers need to be attached or detached during run-time.

For example, after speed negotiation, high speed device needs to enable high speed terminations on both D+/D- lines and needs to remove pull-up resistor from D+ lines.

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