Routing congestion on Stratix® 10 SX SoC FPGA

[joseph_wu]

Hi,

I was trying to compile a large design on Stratix® 10 SX 2800 and got routing congestion issue during "Route" process after routing for 14 hours and finally failed.

I tried some different ways to resolve the issue, but the issue still existed.

1. Adjusted some advanced fitter settings
   • Fitter aggressive routability optimization -> Always
   • Optimize hold timing -> Off
   • Optimize timing -> Off
2. Reduced design size 
3. Splitted top-level design into smaller submodules

I also checked "Intel Quartus Prime Pro Edition User Guide: Design Optimization" and it says coding style might cause routing congestion but does not go deeper on that.

So, I also want to ask what kind of coding style might lead to routing congestion?

Since it took more than 10 hours for one compilation process, I would be appreciated if anyone could offer some pieces of advice.

* "Report routing utilization" heatmap from Chip Planner and fitter resource usage are attached for your reference.

* I ran the compilation on Quartus Prime Pro 20.1 with CentOS 6

Thanks in advance.

Joseph

[SyafieqS]

Hi Joseph,

May I know if there is any other warning/report why is the failing?  

 I also want to ask what kind of coding style might lead to routing congestion?

- Coding style here referred to recommended design practice for Intel FPGA device and Quartus e.g. how you inferred ram,dsp,multiplier etc. Since you are using hyperflex device (S10 and Agilex), they have a different kind of architecture thus different optimization e.g clocking, combi rtl, pipelining etc. Assuming this is a general congestion, you can visualize in congestion report in Compilation Report > Fitter > Route Stage > Global Route. Once you identify where is the congestion are, you can locate in chip planner to further debug, might be due to high fanout, thus you can do so register duplication to reduce the them etc.

Another way according to the document are as below:

https://www.intel.com/content/www/us/en/docs/programmable/683641/21-4/faq.html

1. 4.2.3.6. Guideline: Remove Fitter Constraints

2. 4.2.3.12. Guideline: Reduce Global Signal Congestion

3. 4.2.4.3. Guideline: Increase Router Effort Multiplier

4. 4.2.4.4. Guideline: Remove Fitter Constraints

5. 5.6. Periphery to Core Register Placement and Routing Optimization

You may refer more to below document I attach. I suggest you to refer to Design Recommendations as it will help you with the right technique to optimize the design.

https://www.intel.com/content/www/us/en/docs/programmable/683082/22-1/recommended-hdl-coding-styles.html

[SyafieqS]

Hi,

Let me know if there is any update

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.