Hello all,I'm trying to run the "Small Hello World" example in Nios II by using a DDR2 with the UNIPHY controller both for data and instructions. I'm using a custom preset I've made for a Winbond W971GG6JB DDR2 memory. The vectors for Nios II are set to: * Reset vector: 0x0000000 * Exception vector: 0x0000020 Please, find the current SOPC Builder configuration and my Quartus II top file in the attached figure. My target device is a Stratix IV (EP4SGX230DF29C3). After programming the FPGA and run the software, the Eclipse shows the following message: "Connected system ID hash not found on target at expected base address". If I use an onchip memory both for data and instruction and the DDR2 for data only (as in Altera Application Note 398), it works well. I don't know what I'm doing wrong. Any suggestion will be welcome. Thank you so much for your time. PS: my tools are * Quartus II Version 11.0 Build 208 07/03/2011 SJ Full Version * Eclipse Build id: 20100917-0705
Whenever I've had an issue with this, it's always been something held in reset preventing the read of the system ID. I'd recommend checking their polarities and adding SignalTap if necessary.
Thank you all for your replies.@skaneta: I've checked the reset signal and it's OK. @Socrates: I ran the memory test demo from Eclipse (running Nios on on-chip memory) and it seems to hang on the "IOWR_32DIRECT" instruction. So, I set the start and end addresses for the test, but it does nothing else. I've also checked all the pin assingments and they're OK. Any idea about what it's going on?
I would go the other way:connect external 50MHz clock to DDR2 memory controller. The controller gives outputs of 100MHz and 50MHz clocks. Choose one of them and use it for the whole SOPC system. This means that the external clock is connected only to memory controller and all the other components (including cpu itself) is connected to the memory controller clock output. No need of clock crossing bridge then.
Check to make sure the byte enables are enabled in the Uniphy settings. I'm not sure when it happened but I noticed a few months ago they were disabled when I was using it in Qsys. CPUs don't always perform word accesses so you need those byte enables.Also if you want any kind of performance from that CPU I would put it on the same clock domain as the SDRAM. Even if you have to decrease the SDRAM speed to achieve timing it'll still be much faster than the async. clock crossing SOPC Builder is inserting in your design (~9 extra clock cycles for every read with no back to back accesses)