CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
After power on, FPGA can't load image form flash, the nstatus and nConfig set 1,but CONF_DONE and INIT_DONE set 0 , here is configuration status in SDM tool
From the error state you provided, the issue might be related to OSC_CLK_1. May I know if you are using external clock to performed configuration? Do you provide the correct clock frequency?
Yes,I used external clock with 125Mhz, maybe I should check it. By the way,how can I get the details about States/Error Location/Error Detail parameters ?
