Hello. I am trying to create design with 66b rx and tx data bus widths using L/H Tile Transceiver Native PHY S10
I have read, as I think, everything in documentation but didn't get example of my use case.
I enabled enhanced pcs in ip core, then 64/66 data path, selected pcs clock as div_33... But did not get as i expected when testing
I want 66 bit data path without enable signals, as ip core can work in pma mode 66 bits
I know that 100 GbE IP core generates as i want, or about it
Speed is 25 gbps
P.s. Any help will help!
