Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

SDC Command for set_clock_latency for a specific clock target

Altera_Forum
Honored Contributor II
‎02-26-2016 11:33 AM
1,319 Views

Hallo all, 

 

Could anybody please share the SDC Command for setting clock latency for a "specific target clock". I am unable to find the correct SDC Command.  

 

-6.109(Setup Slack) ; APP-FPGA_Application_Logic:inst1|FilamentControl:inst30|PWM_Gen:inst1|\PWMControl:v_pulse_count_nom[0] ; APP-FPGA_Application_Logic:inst1|FilamentControl:inst30|PWM_Gen:inst1|\PWMControl:v_updatePWMvalue ; 150Mhz_Osc_Clock ; 150Mhz_Osc_Clock ; 6.666 ; 0.369 ; 13.145 ; 

 

I have a negative setup slack for a 150MHz clock in this path and I thought setting up a clock latency might constrain this. Any suggestions? 

 

Thank you!
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.