tLTD value of Arria V FPGA

[Altera_Forum]

Hi, 

 I'm using Arria V series FPGA. In the device datasheet, tLTR (time of the receiver CDR to lock to the ref clock) is specified as maximum of 10 us. But tLTD(time to start recovering valid data) is specified as minimum of 4 us. I can not understand the meaning of minimum value. Does it mean CDR MUST not lock to data within 4 us? How can I get the maximum value of tLTD?  Is the receiving data ALWAYS correct after tLTD?  Thanks. Rico.

[Altera_Forum]

It simply means you must wait at least 4us before trusting the data that comes from the CDR. I too feel the wording is poor. Perhaps more appropriate - 'tLTD is the time to wait for the receiver CDR to start recovering valid data...'. 

   --- Quote Start ---  Does it mean CDR MUST not lock to data within 4 us?  --- Quote End ---   No. However, the data is only guaranteed to be correct 4us after 'rx_is_lockedtodata' signal goes high.    --- Quote Start ---  How can I get the maximum value of tLTD?  --- Quote End ---   Assuming what I've already written is true, this is no longer relevant.    --- Quote Start ---  Is the receiving data ALWAYS correct after tLTD?  --- Quote End ---   Subject to all conditions remaining within the parameters defined in the datasheet - yes - that should hold true.  Cheers, Alex