SDC constraints for DE Boards Audio Codec WM8731

[Altera_Forum]

In examples provided by Terasic there are no constraints for chipset WM8731 for playing/recording audio but when expanding examples I see noise on audio signal recorder from LINEIN and played back to SPEAKOUT. 

 In DE1-SOC I have Audio Codec in Master Mode:  http://www.alteraforum.com/forum/attachment.php?attachmentid=10988&stc=1   And these are constraints from datasheet:  http://www.alteraforum.com/forum/attachment.php?attachmentid=10989&stc=1   This is a 1KHz sine wave generated from audacity, recorded and played by DE1-SOC, then captured with oscilloscope http://www.alteraforum.com/forum/attachment.php?attachmentid=10987&stc=1   and this is noise when there is no audio signal in LINEIN http://www.alteraforum.com/forum/attachment.php?attachmentid=10986&stc=1   This seem a problem with DAC/ADC sampling timings. These are my constraints:  create_clock -name bclk -period 325 set_max_delay -fall_from bclk -to 10 set_max_delay -fall_from bclk -to 35 set_output_delay -clock bclk -max 10 set_output_delay -clock bclk -min 10   But timequest fail because bclk setup violations with main clock  What is missing?  Thanks all

[Altera_Forum]

This is because you need to relate your inputs and outputs to the main clock not bclk. I can't see the table in the second image - too blurry, can you type out what it is saying? Also please post your main clock rate. There are a few things you need to setup like multicycle constraints and generated clock constraints. Also post how you are creating bclk.

[Altera_Forum]

Bigger image of timing diagram: http://it.tinypic.com/r/9foftf/8 

 WM8731 datasheet (pag. 14) say that DACDAT (generated from FPGA) should be have setup and hold relations with BCLK generated from WM8731.  BCLK is not generated by me but is an output of audio codec.  I have a 50 MHz clock that go up to 100 MHz and clock NIOS system. A phase corrected -3ns clock at 100 MHz is generated for SDRAM. Another 50 MHz onboard clock goes up to 18.432 and feed XCK of WM8731.  I use university program audio ip that unfortunately comes without constraints.  WM8731 datasheet: http://www.cs.columbia.edu/~sedwards/classes/2008/4840/wolfson-wm8731-audio-codec.pdf  Why I need multicycle constraints?  Thanks

[Altera_Forum]

OK i see. The WM8731 is supplying the clock. I thought the FPGA was doing that. 

 In that case, you basically have to constrain a source synchronous interface (SDR). In the datasheet the data looks to be center aligned relative to Bclk. So we have to use virtual clock to account for this.  # real clock create_clock -name bclk -period 325 [get_ports BCLK] # virtual clock create_clock -name bclk_launch -period 325 -waveform {162.5 325} # shift the rising and falling edges by 162.5 ns  # then relative to bclk_launch set_input_delay -clock bclk_launch -max 15 [get_ports ADCDAT] set_input_delay -clock bclk_launch -min 0 [get_ports ADCDAT]  set_output_delay -clock bclk_launch -max 10 [get_ports DACDAT] set_output_delay -clock bclk_launch -min -10 [get_ports DACDAT]   I'm not sure if this will work, give it a try.

[Altera_Forum]

Works bu the problem is that today.. works also without constraints.. :(

[Altera_Forum]

So are you getting clean signals right now?

[Altera_Forum]

Yes, with and without constraints.. This seem a PVT (process, voltage, temperature) variance problem that design can not manage without proper constraints but now is difficult (time consuming) to check if your constraints are fine..

[Altera_Forum]

Mmm.. I am checking all parameters of project and under Setting /Operating Settings and Conditions/Voltage there are a lot of parameters with wrong voltage that don't reflect real schematic! I don't think this change things but is a bad thing for golden_top of DE1-SOC

[Altera_Forum]

I have the DE2-115 board that has the same WM8731 circuit. They also didn't provide a constraints file for the audio signals... You are probably going to have to write the timing file yourself.

[Altera_Forum]

Yes, I got same conclusion :)