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Valued Contributor III
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SDC problem

hi, 

My requriement is that: 

There are two input signal, In_a, In_b, these two signals will be connected to clock and data (llike I2C). two output signal, Out_clock, Out_data.  

Because the In_a could connect to clock or data, so i need write a module to identify which one(clock or data) will connet to In_a, then re-arrange the order and output the correct signal , i.e. Out_clock or Out_data. 

 

the code is like this: 

 

module Switch(input wire In_a, input wire In_b, input wire S, output wire Out_clock, output wire Out_data) 

begin 

assign Out_clock = S ? In_a : In_b; 

assign Out_data = S ? In_b : In_a; 

end 

 

if S is connected to external pin, the maxmum frequency is 200Mhz. 

 

if i write a module to generate control signal S by In_a and In_b, for example like this 

module Identify( input wire In_a, input wire In_b, out reg S) 

begin 

//some statistic code to indetinfy ....... 

end 

 

the maximu frequency is 30Mhz. 

 

The problem is: 

I want the signals from In_a and In_b to Out_clock and Out_data can run at 100Mhz. the module Identify will influence the frequency(tsu). I want to write a SDC file to optimize the maximu speed. 

the Identify moule just generate signal S to pick up which one is clock. if the S is ready, it is latched and needn't changed again . the data can be discarded before the S is generated. 

 

So, how can i do this ? 

 

will set_max_delay -from -to affect? 

 

best ...
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3 Replies
Highlighted
Valued Contributor III
6 Views

 

--- Quote Start ---  

hi, 

My requriement is that: 

There are two input signal, In_a, In_b, these two signals will be connected to clock and data (llike I2C). two output signal, Out_clock, Out_data.  

Because the In_a could connect to clock or data, so i need write a module to identify which one(clock or data) will connet to In_a, then re-arrange the order and output the correct signal , i.e. Out_clock or Out_data. 

 

the code is like this: 

 

module Switch(input wire In_a, input wire In_b, input wire S, output wire Out_clock, output wire Out_data) 

begin 

assign Out_clock = S ? In_a : In_b; 

assign Out_data = S ? In_b : In_a; 

end. 

--- Quote End ---  

 

 

Someone else might have a better idea, but I'd treat both signals as tied to a virtual 100 MHz clock and use that in the set_input_delay for both of the signals. The question is where the first latch is going to be, and how you want to register these signals. set_input_delay can create the relationship between the virtual clock and the FPGA-based clock, but as of now you have two signals that are unregistered. 

 

Maybe consider a fast_input_register setup on each of them latched to the FPGA clock before doing anything else to them to get known signal timing? 

 

Also, if one of these clocks is actually going to be used as a clock, that means the out_clock should be in the SDC as a virtual clock in the system. 

 

Hopefully others with more experience can provide some better resources.
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Valued Contributor III
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My stupid method is Identify module output the S to external pin, and route this pin back to another pin. 

Then use this pin to control Switch module. 

 

The Quartus don't know the relationship between S from external pin and In_a, In_b, the synthesized module can run at 200Mhz. 

The key is to disconnect relationship between S and In_a, In_b. The method is using external pin. 

But i feel that this method is very stupid.
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Highlighted
Valued Contributor III
6 Views

 

--- Quote Start ---  

My stupid method is Identify module output the S to external pin, and route this pin back to another pin. 

Then use this pin to control Switch module. 

 

The Quartus don't know the relationship between S from external pin and In_a, In_b, the synthesized module can run at 200Mhz. 

The key is to disconnect relationship between S and In_a, In_b. The method is using external pin. 

But i feel that this method is very stupid. 

--- Quote End ---  

 

 

I don't understand why you would do this-- S is already internal, and there has to be a known relationship because you know your FPGA clock. Even if that is set using set_false_path, you can build up the timing network.
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