SDC syntax for declaring generated clocks

[Altera_Forum]

Hello, 

  Below, I have pasted a module that i have created. Now, i want to declare the outputs of this module as clocks in the SDC constraint file.  entity CLKCTRL is  Port ( -- Clock  CLK : in std_logic;  -- Reset  RESZ : in std_logic;  -- System Bus Clock Divider Value  BUSDIV : in std_logic_vector(1 downto 0);  -- Output 0 Clock Divider Value  O0DIV : in std_logic_vector(5 downto 0);  -- Output 1 Clock Divider Value  O1DIV : in std_logic_vector(5 downto 0);   -- System Clock  HCLK : out std_logic;  -- Output 0 Clock  O0CLK : out std_logic;  -- Output 0 Inverted Clock  O0CLKZ : out std_logic;  -- Output 1 Clock  O1CLK : out std_logic;  -- Output 1 Inverted Clock  O1CLKZ : out std_logic); end CLKCTRL;  architecture Behavioral of CLKCTRL is  -- System Clock Counter signal count_HCLK : std_logic_vector(1 downto 0);  -- Output 0 Clock Counter signal count_O0CLK : std_logic_vector(5 downto 0);  -- Output 1 Clock Counter signal count_O1CLK : std_logic_vector(5 downto 0);  -- System Clock signal s_HCLK : std_logic;  -- Output 0 Clock signal s_O0CLK : std_logic;  -- Output 1 Clock signal s_O1CLK : std_logic;  begin   -- Based on the Value of BUSDIV  -- System Clock is selected    HCLK <= CLK when BUSDIV = "00" else  s_HCLK;   -- Based on the Value of O0DIV  -- Output 0 Clock is selected   O0CLK <= CLK when O0DIV = "000000" else  s_O0CLK;   -- Based on the Value of O0DIV  -- Output 0 Inverted Clock is selected   O0CLKZ <= not CLK when O0DIV = "000000" else  not s_O0CLK;   -- Based on the Value of O1DIV  -- Output 1 Clock is selected   O1CLK <= CLK when O1DIV = "000000" else  s_O1CLK;   -- Based on the Value of O1DIV  -- Output 1 Inverted Clock is selected   O1CLKZ <= not CLK when O1DIV = "000000" else  not s_O1CLK;    p_1: process(RESZ, CLK)  begin  if RESZ = '0' then  count_HCLK <= (others => '0');  count_O0CLK <= (others => '0');  count_O1CLK <= (others => '0');   s_HCLK <= '0';  s_O0CLK <= '0';  s_O1CLK <= '0';   elsif CLK'event and CLK = '1' then   -- Clock Generation for System Clock   if count_HCLK >= conv_std_logic_vector(((conv_integer(BUSDIV)+1)/2),2) then   if count_HCLK = BUSDIV then  count_HCLK <= (others => '0');  else  count_HCLK <= count_HCLK + 1;  end if;   s_HCLK <= '1';  else   count_HCLK <= count_HCLK + 1;  s_HCLK <= '0';  end if;   -- Clock Generation for Output 0 Clock   if count_O0CLK >= conv_std_logic_vector(((conv_integer(O0DIV)+1)/2),6) then   if count_O0CLK = O0DIV then  count_O0CLK <= (others => '0');  else  count_O0CLK <= count_O0CLK + 1;  end if;   s_O0CLK <= '1';  else   count_O0CLK <= count_O0CLK + 1;  s_O0CLK <= '0';  end if;   -- Clock Generation for Output 1 Clock   if count_O1CLK >= conv_std_logic_Vector(((conv_integer(O1DIV)+1)/2),6) then   if count_O1CLK = O1DIV then  count_O1CLK <= (others => '0');  else  count_O1CLK <= count_O1CLK + 1;  end if;   s_O1CLK <= '1';  else   count_O1CLK <= count_O1CLK + 1;  s_O1CLK <= '0';  end if;   end if;  end process p_1;   end Behavioral;   Regards, Anil.

[Altera_Forum]

The following documents will help you set up time constrants in SDC for you design  

 http://www.altera.com/literature/hb/qts/ug_tq_tutorial.pdf - TimeQuest Analyzer Tutorial  http://www.altera.com/literature/hb/qts/qts_qii53018.pdf - The Quartus II TimeQuest Timing Analyzer  Cheers  Rob Morley

[Altera_Forum]

Be careful about driving clocks with logic resources. Something like a clock divider is better done with a PLL if you have a PLL available or with a clock enable. 

 I have a post at http://www.alteraforum.com/forum/showthread.php?t=453&highlight=clock+enable with some considerations if you do use logic resources to do the clock division.

[Altera_Forum]

Hi Brad, 

  Thanks for your reply. I have checked your post. But i have some problems. I cannot use PLL's. I just have a clock and i need to divide this directly. Now, how can i use a clock enable to get a divide by 1 or 2 or n clock , with approx 50% duty cycle.   if this not possible. Let me know, how i can assign this divided clock to a global assignment. Because this doesn't exist on my top level entity for the FPGA.  Regards, Anil.

[Altera_Forum]

To do a divide by n, you create a signal that pulses every nth clock cycle (the signal is asserted for one full clock cycle out of every n clock cycles). That signal is used as the clock enable. The registers running at the slower speed with that enable are clocked by the full-speed clock signal; the enable gives the same effect as using a slower clock. You can use multicycle exceptions in TimeQuest to say that any path between clock-enabled registers is allowed n clock cycles for setup. 

 The Quartus II version 7.1 handbook shows how to describe the clock enable in HDL. Volume 1, Section II, Chapter 6, Example 6-31 has a VHDL example with a clock enable together with other control signals that you can omit if you don't need them. You need the nested "if" that describes the enable inside the "if" that detects the clock edge.   Here's an example of a way to create the multicycle exceptions for a divide by n (set to divide by 4 in the example). This example uses get_fanouts to apply a single pair of setup and hold exceptions to all paths where the source and destination registers both use the same clock enable. The set_multicycle_path -from and -to fields each contain the full set of registers using the clock enable. TimeQuest will apply the multicycle exceptions to all the paths that actually exist between all possible pairings of these registers. When you use the clock enable resource in silicon, it is OK if the new data actually arrives at the destination sooner than the n clock cycles. The multicycle hold of n-1 tells TimeQuest that the old data does not have to be held during the clock cycles when the clock enable is deasserted.  set all_enabled_registers ] set clock_enable_divide_by_n 4 set_multicycle_path -setup $clock_enable_divide_by_n -from $all_enabled_registers -to $all_enabled_registers set_multicycle_path -hold -from $all_enabled_registers -to $all_enabled_registers