SDR to DDR timing constraint conversion

[Altera_Forum]

Hi, 

 My design uses classic timing analyser and I have the following constraints for a SDR source synchronous interface.  tsu_requirement/th_requirement for input and tco_requirement/min_tco_requirements for the output  I have made the interface DDR now and what changes will I have to make to the above constraints? The HW (trace delay etc) remains the same. How do the above constraints get modified for a DDR i/f?  How do I confirm that the design would meet timings on DDR as well?  For some reasons, I cannot upgrade my constraints and have to work with the above.  Regards, Satish

[Altera_Forum]

In general, the problems with Tsu/Th/Tco, like the fact that they basically ignore the difference between rising/falling edges, works in the favor of DDR interfaces, and actually makes it easy. Just use what you have, knowing it will apply to both edges, and you should be all right.

[Altera_Forum]

Thanks Rysc for resolving my concern.