SDRAM calibration errors with .jic file

[anonimcs]

Hi all,

I have a design on Arria10 and I'm using QP 21.3 Pro for development. In the design there's an HPS and an EMIF to DDR4 for that HPS. I've realized that when I program the FPGA with .sof file, everything works fine and the HPS boots up, however when I program the .jic file and then power cycle the board, the HPS doesn't boot up, and I get the following error.

U-Boot SPL 2021.07 (Dec 02 2021 - 03:12:39 +0000)
Error: Could Not Calibrate SDRAM
DDRCAL: Failed
WDT:   Started with servicing (10s timeout)
Trying to boot from MMC1

Anyone knows what the reason for this can be ?

Kind regards

[Farabi]

"We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

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[Farabi]

"We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding."

[Farabi]

Hello,

The issue you’re encountering suggests a potential problem with the DDR4 calibration process during the HPS boot-up from flash memory (via the .jic file). When the FPGA is programmed via the .sof file, the DDR4 interface configuration and calibration are likely handled correctly, but the .jic programming (which includes both the FPGA and HPS firmware) may be missing some key configuration or initialization data. Below are some possible reasons and steps to resolve the issue:

---

1. **DDR4 Calibration Data Missing in Flash:**

  - The .jic file might not include the proper DDR4 calibration data, which is needed during HPS boot-up.

2. **Boot Settings Misconfiguration:**

  - The boot mode settings in the HPS might not be correctly configured for booting from the specific flash memory (e.g., QSPI).

3. **Mismatch in FPGA Configuration and HPS Bootloader:**

  - The FPGA configuration in the .jic file may not be synchronized with the HPS U-Boot SPL used in the system.

4. **Power-On Reset Timing Issue:**

  - The HPS and FPGA reset sequences may not be properly aligned, causing issues in initializing the DDR4 interface.

5. **Incorrect Device Tree or Preloader Settings:**

  - Errors in the device tree or preloader configuration might cause DDR4 initialization to fail during boot.

---

Steps to solve this issue:

1. **Regenerate and Include Calibration Data:**

  - Ensure the DDR4 calibration data generated by the EMIF IP is included in the HPS preloader or FPGA configuration. Rebuild the preloader with updated EMIF configurations.

  - In the Quartus Pro settings, verify that the EMIF configuration is exported correctly.

2. **Verify Boot Mode:**

  - Check that the HPS boot mode switches/jumpers are correctly configured to boot from the intended memory (e.g., QSPI or MMC).

3. **Update and Synchronize U-Boot and Preloader:**

  - Rebuild the HPS preloader and U-Boot with the latest configurations.

  - Ensure the generated preloader binary is compatible with the .jic file and that the DDR4 settings are consistent between the FPGA and HPS.

4. **Check Reset and Power Sequencing:**

  - Review the reset configuration in Platform Designer (Qsys) and ensure that the HPS reset is properly synchronized with the DDR4 initialization.

5. **Test with a Known Good Device Tree:**

  - Verify the device tree includes the correct configuration for DDR4. Use a reference design's device tree and modify it for your setup if necessary.

6. **Generate and Program a Unified .jic File:**

  - Make sure the .jic file includes all necessary components: the FPGA configuration, HPS preloader, and other bootloader components.

  - Use the Intel Quartus Convert Programming File tool to generate a combined .jic file that includes the necessary configuration for both the FPGA and HPS.

7. **Check for Hardware Issues:**

  - Verify signal integrity and power stability on the DDR4 and HPS interfaces. Ensure that all required power supplies are stable and within specification during the boot process.

---

regards,

Farabi

By carefully checking these aspects, you should be able to resolve the issue and ensure successful HPS boot from the .jic file. If the problem persists, providing additional logs or configuration details could help in further diagnosing the issue.