Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

SHA-1 algorithm

Altera_Forum
Honored Contributor II
1,275 Views

Hello! 

 

I'm working on a implementing the hash algorithm SHA-1. I know might be a bit of a longshot to ask about that here, but I'll give it a try. 

 

I've been trying to implement the algorithm using the following two documents: 

http://www.ietf.org/rfc/rfc3174.txt 

http://signal.hut.fi/~kjarvine/documents/sha.pdf 

 

In SHA-1 there is a message to be hashed, the message is padded to blocks of 512 bits width. The algorithm then has 80 steps to calculate the hash for each 512 bit block.  

 

The first sixten steps a different 32-bit word is taken from the 512 bit block, called w_t where t is 0:15. What I'm not entierly shure of is if w_0 is the 32 most significant bits or the 32 least sigificant bits of 512 bit block. 

 

Best regards, 

Ola Bångdahl
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
513 Views

w_0 is the most significant bit. 

suppose you have entered 'abcdefgh' then the w_0 will store 'abcd'.
0 Kudos
Reply