Delay between Input pin to output pin via single LE

[Altera_Forum]

Dear sir, 

 We want to know the signal delay between input pin to output pin via a Logic Element inside Cyclone-IV E FPGA.  Please help.  Regards, Thulasi

[Altera_Forum]

This will depend on which input pin, which output pin and which logic element you use. 

 Regards, Alex

[Altera_Forum]

Dear sir, 

 Is there any document which mentions the minimum & maximum propagation delay of Cyclone IV E. I was getting in the order of min 4ns & max 7ns from Timequest analyzer without implementing any logic between input & output inside FPGA. I am trying to configure both input & output in the same bank.  We want to know what is the order of propagation delays(min, max) between input to output when the input travels through output without any logic.  Please help in this direction. Regards, Thulasi

[Altera_Forum]

Refer to the timing closure and optimization (http://www.altera.com/literature/hb/qts/qts_qii52005.pdf) datasheet for a wealth of information regarding timing. 

 This will discuss pin to register delays and register to pin delays as well as register to register timing. The key stats required to allow you to ensure a synchronous design meets timing.  However, I'm not sure it'll give you numbers you're after.  All I can confirm is that the figures you state TimeQuest offers sound about right. If you are simply using the FPGA as a buffer (something it's not very good at) then, depending on pin placement, I think you should expect anything from 2ns to in excess of 7ns. If the input pin happened to be a dedicated clock input, you might expect different figures.  Regards, Alex