Shifted clock signal when connecting to FPGA (cyclone iii)

[Altera_Forum]

Hello, I am getting some strange behavior that I can't understand what would be causing the behavior. I have a 32MHz crystal oscillator that I've been trying to use as a digital clock signal to drive my logic in a EP3C40 cyclone III fgpa. I've scoped my clock signal when the output is floating and it appears to be sinusoidal with a low of about 300mV, and high of 3.2V (not a clean looking digital clock signal unfortunately).. Perhaps this is the underlying problem for what behavior I see.. anyways... Although it is sinusoidal i thought this might end up triggering high and low levels at user I/O pins anyways and that I could still be able to use the signal to drive some logic. I was actually planning to down sample the clock by generating an output clock line on another user I/O pin and just use an internal signal/register for latching 'highs' from my input I/O pin.. Here's my VHDL code below to go from AC 32Mhz clock to digital 16Mhz output clock: 

  library IEEE; use IEEE.std_logic_1164.all;  -- Signal clock for Toshiba TCM8230MD -- 30MHz for ~ 30fps.. => 33ns cycle ENTITY clk IS  PORT (clk_in: IN std_logic;  clk: OUT std_logic); END clk;   --Arch ARCHITECTURE behavioral OF clk IS  signal clk_internal : STD_LOGIC := '0'; BEGIN --clk <= clk_internal;  PROCESS  BEGIN  WAIT UNTIL rising_edge(clk_in);  IF (clk_internal = '0') THEN  clk <= '0';  ELSIF (clk_internal = '1') THEN  clk <= '1';  ELSE  clk <= 'Z';  END IF;  clk_internal <= NOT clk_internal;  END PROCESS; END behavioral;    So i realize that this possibly may not work anyways as Quartus may just try to pass the signal through to the output so if it's seeing an AC signal, it'll just pass that through to the output as some distorted digital clock signal...  Aside from that however, once I've actually connected my clock signal to any one of my user I/O pins (via a female header connector) and I scope out the signal, the DC bias is offset up higher so that my swing is actually something like 1.8V - 4V about. I have seen this when my board is powered on and disconnected from any power.. I guess I could understand if the bias was offset upwards if the power was on and there is some sort of internal pull up circuitry going on to the VCCIO (in my case 3.3V on all my I/O banks). But the fact that I get this same behavior when the board has no power supplied is making very confused.. I guess I would have just expected a shift down without power if anything.  Has anyone else seen this type of behavior before with FPGAs or anywhere else? Any help or guidance for what else to look at is much appreciated! Alternatively... anyone have a decent clock IC for 3.3V logic and schematic to go along with it??? This is just a hobby board i've scrapped together, but I would love to get this thing finally working..  Thanks!! ~doddy   EDIT1-2/18/2014: I should also mention that my output with the code and clock source applied is just 3.3V with a lot of noise on it.

[Altera_Forum]

Logic generated clocks are not recommended and liable to being rubbish. You should use a pll as you have much more control over the generated clock. Logic clocks can be affected by things like routing delays and temperature, which you have little control over.

[Altera_Forum]

Thank you for your reply. Could you direct me to a handbook/user guide on how to use the pll properly (or global clock) that is generated via a dedicated input clock pin? I looked into the Timing Wizard in Quartus but I wasn't sure if this is where to look to generate the PLL output.

[Altera_Forum]

PLLs can be generated via the megawizard. see the PLL documentation on the altera website 

http://www.altera.co.uk/literature/ug/ug_altpll.pdf

[Altera_Forum]

Perfect, I'll have a look here! Thank you.

[Altera_Forum]

I've tried using the megawizard now but I am getting the same results. In Quartus II (web version 11.0) I clicked Tools->MegaWizard Plug-In Manager. I followed along with one of the examples in the ug_altpll.pdf file to do something similar for a single clock in and single clock out line (I opted out to not use a locked pin or feedback 'fbin' pin). I made necessary changes to use Cyclone III device instead of Stratix device as used in the example. When I completed the wizard, I generated a VHDL file which I used for a project with 2 pins. I assigned the input 'clkin0' port to input pin 149 of my device (DIFFCLK_3n) and output 'clk' port to output pin 240 of my device (PLL3_CLKOUTp). 

 I compiled the design, with no errors and no critical warnings. I then powered up and programmed my fpga on my board and then turned on my oscillator signal applied to pin 149. Scoping the output I see the same results as what I had seen with just regular user I/O pins (Basically the output is a high 3.3V signal with lots of noise). So it seems like the triggering is still not happening on rise and fall of my clock signal but somehow the noise is passing through.  In the assignment editor I've chosen 3.3V LVCMOS as my logic levels. This is consistent with my VCCI/O however perhaps I should chose 2.5V for my PLLs as I know 2.5V is used to power the PLL lines through a choke/ferrite bead (VCCA1 - VCCA4 is 2.5V, VCCD_PLL1 - VCCD_PLL4 is 1.2V).  Is there a way to select the 'optional pin function' for the pins I am using? When looking at the pinout information for Cyclone III devices there is a column for Pin Name/Function and then another column for Optional Function(s) so perhaps I need to make that selection somewhere in the assignment editor or somewhere else?  I hope I was able to explain myself clearly. Any suggestions are welcome! Thanks.   Edit1 3/4/2014: I forgot to mention also, my clock source looks like an AC waveform (fairly clean looking but not square wave at all). Is that a problem for triggering high and low levels? It ranges from 0-2.3V which according the the cyclone iii spec should trigger the Vih and Vil for 3.3V LVCMOS. But perhaps i'm missing something here. I should maybe use TTL?

[Altera_Forum]

So I have scoped out several I/O and dedicated CLK pins on my board. I've noticed that just looking at a pin I see a DC voltage of around 1.12 Volts. Is it possible that my FPGA is damaged? This to me seems like I'm seeing the VCCINT voltage (1.2V) with a small voltage drop. I'm not familiar with the architecture internal to the FPGA but to me this looks like the control circuitry could be fried and now I'm just seeing the internal power being applied at the I/O pins. This is definitely the shift I'm seeing in my clock line as well. 

 Any suggestions?