10-20-2017 09:59 AM
Hi all,Is it possible connect a SPI ram (single or quad) to the NiosII in Qsys and allocate/use (from C code in Eclipse) my data in this ram? Thanks in advance. Perryiavo
10-20-2017 11:24 AM
Hi Perryiavo,Apologize in advance since I’m not really expert in NIOS application. However as far I know in general, it is possible to use an external RAM with Nios II to execute your data/C code. You can refer to the AN730 on this: https://www.altera.com/en_us/pdfs/literature/an/an730.pdf Regards, nyusof (This message was posted on behalf of Intel Corporation)
10-20-2017 12:56 PM
--- Quote Start --- Hi Perryiavo, Apologize in advance since I’m not really expert in NIOS application. However as far I know in general, it is possible to use an external RAM with Nios II to execute your data/C code. You can refer to the AN730 on this: https://www.altera.com/en_us/pdfs/literature/an/an730.pdf Regards, nyusof (This message was posted on behalf of Intel Corporation) --- Quote End --- Yes, I have already seen that document but my problem is to communicate with the ram on SPI. I would make a bridge between avalon MM bus and SPI. Is it possible? If yes, how? Thanks.
10-29-2017 02:26 PM
Hi Perryiavo,Again, apologize in advance since I’m not the expert in NIOS application. I think you can use the SDRAM IP together with the NIOS II in the Qsys to communicate with the external RAM memory. Refer to the Embbededd IP user guide from the following link for the SDRAM IP usage: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf Regards, nyusof (This message was posted on behalf of Intel Corporation)
11-02-2017 12:55 PM
The OP is talking about an SPI ram, not an SDRAM. None of the documentation you pointed to is relevant.As far as I know there isn't any ready available module for what you want to do. If you use a generic SPI master IP, you will have to write a software driver and manually send commands to the RAM and read back the results. If I understood your post correctly, you'd rather like a hardware module that will make the SPI ram directly available to the Nios II CPU as if it was a regular RAM. I'm afraid you will have to write this yourself.
04-23-2018 03:12 PM
Yes,I would like a hardware module that allows NiosII to see the external SPI ram as regular RAM (obviously slower then a real RAM). I resolved this problem: I wrote my hardware module (in VHDL) and I used a Avalon-MM Pipelined Bridge to export the Avalon-MM bus to this module (extern to NiosII). This module manages on one hand the interfacing with NiosII (raises the waitrequest signal in order to stop the execution of the code until it has completed the operation with external RAM, asserts data for the read operations etc. etc.) and on the other hand manages the communication from/towards the external SPI ram according to the rules of the ram itself. In the application code of NiosII (C code) I allocate in the address space provided by the Avalon-MM Pipelined Bridge the variables, the stack and all the rest of my application (apart from the exception code that I run in the internal ram for reasons of execution speed). Regards, Perryiavo.