I have to implement an SPI slave module in a small Max II device. The module will be used to load values into some registers and read values from others. The main clock of the CPLD is 1 MHz and I wonder about the maximal SPI clock rate I can support.
My SPI signals are the standard SCK, SSn, MOSI and MISO, and SCK is driven by the microcontroller. Let's say that data is driven on rising SCK and read on falling SCK.
I basically have 2 directions to take here:
1. Synchronize SCK to my internal clock. That means a 2-cycle (@1MHz it's 2 us) delay, so when I see a rising SCK, it's 2 us late. Then in order to make it to the falling edge so that the MCU will read the data, it seems that SCK must be at least 8 times slower than my internal clock. Is this correct?
2. Run the SPI slave module clocked by SCK. This introduces serious synchronization problems, though, as I'll have to synchronize data from SPI into my registers and back on every transaction. This is complex and could use more resources, but allows to run a faster SCK.
Do you have experience with these design decisions? What is the recommended direction to take here?
Thanks in advance
