SRIO and PCIe in Cyclone IV GX

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

SRIO and PCIe in Cyclone IV GX

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There is only 1 transceiver block in Cyclone IV GX model (EP4CGX150CF23C7) 484 pin device. Can I use PCIe hard IP block(in 2x lane mode: channels 0 and 1) and RapidIo megacore block (in 1x mode: channel 2) simultaneously? If yes, how do we deal with ALTGX_Reconfig megacore block?

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