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Is there any quick way for me to check the simultaneous switching noise (SSN) effect on the I/Os of my FPGA, through simulation etc?
Regards, CWLink Copied
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Altera does have a Stratix II SSN simulation kit, but you would need to obtain that through your FAE.
For Cyclone and Cyclone II, there are no models, but you can obtain the characterization data to estimate worst case affects on your design. This is also available through your FAE.
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