SSTL-2 Class I outputs with 8mA drive strength?

[Mark13]

Ì am using a NIOS-processor in a Cyclone IV EP4CE55F23I7N. Connected to the FPGA is a DDR-SDRAM with differential clock input. The clock is outputted from FPGA via SSTL-2 Class I outputs. If no external series resistors are used for those in the Cyclone IV hand book the use of 50 Ohms OCT is recommended together with 50ohms parallet against VTT. Is there a reason against using 8mA output drive strength instead of 50 Ohms OCT? The clock seems to be better with that setting. On some boards I get sporadic PLL-lock losses that do not appear with 8mA drive strength.
Best regards
M.B.

[EngWei_O_Intel]

Hi there

Table 6–2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pd... shows the available current strength setting for different IO standard. It also stated that when you use programmable current strength, on-chip series termination (RS OCT) is not available. Those are the optimum setting done by the characteristic team.

We can refer to below link for more information:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

Thanks.

Eng Wei