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Two clock domains in the same procces

EEren
Beginner
184 Views

The module clock is CLK = 120 Mhz.

The milliseconds counter clock is MS_CLK = 100 Mhz.

I count milliseconds

constant TICKS_FOR_1MS : std_logic_vector(31 downto 0) := X"000186A0"; --100 Mhz
process (MS_CLK)
begin

    if (rising_edge(MS_CLK)) then
        
         if (count_reset= '1') then
             ticks_counter <= (others => '0');
             ms_counter <= (others => '0');
         else
            ticks_counter <= ticks_counter + '1';
            if (ticks_counter = TICKS_FOR_1MS) then
                  ticks_counter <= (others => '0');
                  ms_counter <= ms_counter + '1';
            end if;
        end if;

    end if;   
end process;

The problem is - the signal count_reset is changed in another process that clocked with CLK. How to synchronize those signals?

0 Kudos
2 Replies
EngWei_O_Intel
Employee
134 Views

Hi there

 

I can't fully visualize how the count_reset being used in another process, from your description, seems like you are changing a signal in two different processes which is not a common practice.

 

thanks,

Eng Wei

EngWei_O_Intel
Employee
113 Views

Hi user

We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei

 

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