[STARTIX III][ALTPLL RECONFIG][ALTPLL] Is it possible to change multiplication factor

[Altera_Forum]

Hi there, 

 I need to create a clock with a frequency range from 10MHZ to 30MHZ, with a step of 0.25MHZ. I imagine using an alt_pll and a alt_pll_reconfig Ips.  pll_clk with an input clock set to 100MHZ and one output clock c0. A fixed division factor set to 400. A first divisuion factor set to 40, to obtain 10MHZ.  Then, my question is : is it possible to change (on the fly) the multiplication factor using the pll_reconfig ? If yes i can generate all the needed frequency. M factor = 40 => Foutput = 10MHZ M factor = 41 => Foutput = 10.25MHZ M factor = 42 => Foutput = 10.5MHZ etc ...  I don't want to change any other parameter of my clock.  I read the Altpll_reconfig User Guide and the AN454, but not able to understand clearly if it is possible.  Thanks for your help.

[Altera_Forum]

It's possible, we always use it. But you may have problem with range: very slow freq from 100 MHz.  

Whether or no, you must recompile your design with each step of freq. After each recompile you have to open fitter usages to see PLL options (rewrite it). After that you will have array of PLL parameters for each step. And you may create scan chain for every step from you array. You may use alt_reconfig or write scan chain by you self, never mind...  Good Luck! Anton

[Altera_Forum]

One more, you may see in simulator (Altera ModelSim) all changes of freq reconfiguration

[Altera_Forum]

Ok thanks for you reply. I'll try this.