Security Features of MAX 10 FPGA Internal Flash

[RonSegev]

Hello,
I’m looking for more information about the security design features of the internal flash in MAX 10 FPGAs. Specifically:
1. Can read, write, and erase operations be disabled via JTAG or the On-Chip Flash Intel FPGA IP?
2. Are there alternative methods to read, write, or erase CFM files from the FPGA besides JTAG and the On-Chip Flash IP?

I’m particularly interested in ways to ensure the internal flash remains secure from unintended access or modification. Any insights, documentation references, or best practices would be greatly appreciated!
Thanks!

[Farabi]

Hello,

You can refer to link : https://www.intel.com/content/www/us/en/docs/programmable/683865/current/configuration-design-security.html

for MAX10 design security features.

regards,

Farabi