Serdes in Cyclone 5 devices

[Altera_Forum]

I have implemented a deserializer in Cyclone 5. We see some issues in the final system output (video to a monitor). One of the other engineers here thinks the Serdes in this particular variant (E) of the device is soft (logic element based) but the only documentation I can find is that Cyclone 5 devices use dedicated serdes logic. 

 Can anybody out there verify if the serdes is hard or soft? Is there a way to determine it from synthesis results or Timequest reports?  Thanks.

[Altera_Forum]

You need to be a little more specific.  

 What type of SERDES, eg., an LVDS or a transceiver based SERDES? The E variants do not have transceivers, so I assume you mean LVDS.  In many of the Altera device families, whether or not the LVDS I/O cell contains a SERDES depends on the I/O pins you've selected, i.e., dedicated LVDS I/Os contain either a TX or RX SERDES but not both.  A search of the Cyclone V handbook indicates these devices do have LVDS SERDES, eg., p55 of the PDF, see Figure 5-34: LVDS SERDES  http://www.altera.com/literature/hb/cyclone-v/cyclone5_handbook.pdf  The width of the data bus into the SERDES block is 10, so that indicates the Cyclone V devices support a SERDES of up to 1:10 or 10:1.  If you post details on the device part number and your pin assignments, forum members can comment on whether you have selected an LVDS SERDES appropriately.  Cheers, Dave

[Altera_Forum]

Yes, you are correct, LVDS SERDES. We definitely have selected the LVDS SERDES correctly. 

 I may be confusing what "dedicated" serdes logic means. Documentation says Cyclone 5 has dedicated logic. What I'm after is DPA capability. Looks like that is not an option for this device. The document you linked shows that in Dec. 2012, they removed DPA support.

[Altera_Forum]

--- Quote Start ---   I may be confusing what "dedicated" serdes logic means. Documentation says Cyclone 5 has dedicated logic.   --- Quote End ---   That basically means they have a high-speed shift-register hard-IP block.    --- Quote Start ---   What I'm after is DPA capability. Looks like that is not an option for this device. The document you linked shows that in Dec. 2012, they removed DPA support.  --- Quote End ---   Ok, I see that same note.  The Stratix series devices have DPA. A quick search in the Arria V handbook shows they have it too.  If you do not need dynamic phase-shifting, but do need some sort of power-on alignment, you could also consider using the ALTPLL_RECONFIG block and shift the phase of the ALTLVDS PLL (you can configure the ALTLVDS component for external PLL mode).  Cheers, Dave

[Altera_Forum]

Yeah, I know Stratix has it. Unfortunately board designed already and we discovered we needed the DPA after the fact. (Design criteria changed.) Trying to find a way around it but definitely need something DPA like. Tough one.

[Altera_Forum]

--- Quote Start ---  Unfortunately board designed already and we discovered we needed the DPA after the fact. (Design criteria changed.)  --- Quote End ---   Ah, that is unfortunate :(    --- Quote Start ---   Trying to find a way around it but definitely need something DPA like. Tough one.  --- Quote End ---   What is the requirement? Perhaps the ALTPLL_RECONFIG with dynamic phase-shift control can be useful?  For example, assuming you need DPA to find the center of the eye for your received data, will the phase of that data be changing with time? And if yes, how fast will it change?  If the communication channel is not used 100-percent of the time for "data", you could send training data/idle data, and use the PLL phase-shifts to check that the eye is still optimal.  Cheers, Dave