Serializing Avalon-ST over XCVR for FPGA-to-FPGA Transmission

[Altera_Forum]

I would like to know what options are available for serializing Avalon-ST video data over high-speed XCVR for tranmission between two FPGAs with lowest latency? I have a set of HD resolution video interfaces (VGA, DVI, SDI, etc.) available on one FPGA but I want make them also available to a 2nd FPGA. I assume by using XCVR I can reduce the FPGA-to-FPGA pincount while maintaining the data bandwidth. But I'm not sure what XCVR mode I should use. 

 I am open to alternate suggestions as well.  Thanks in advance!

[Altera_Forum]

Hi, 

 The mode of XCVR to use will be depending on your target data rate, interface width, refclk and etc. If you are looking for a ready-make solution, you can try to look into Altera IP cores ie SDI IP and etc to see if can find one that suit you.

[Altera_Forum]

You'll want to use a mode that incorporates the 8/10B encoder. This makes recovering bytes out of the serial data stream trivial, and supports mismatched data rates through the use of IDLE codes. 

 I have not used it, but I am pretty sure the SerialLite core is for light-weight chip-to-chip communications. Xilinx have a similar protocol called Aurora. I don't know how compatible these two protocols are. Perhaps someone who has used them can comment.  You should "do the math" to determine what sort of bit-rate you require, what sort of lane rate you think your PCB can handle, and hence how many SERDES lanes you will need.  Cheers, Dave

[Altera_Forum]

Hi mbp2014, 

 You can also visit the Altera wiki page, look for transceiver category for the PHY level design example. They will serve as a good start with the Altera transceivers.