Hello, if some one tracks my messages might now, that i am working on high speed data aqusition system for linear CCD.
Finlay i get to a state that i have only one single problem, and i need help with that.
Problem is simple, i have unknown length trigger pulse (1ns-5us) that should start CCD readout. What i need is to be able to make that signal as short as possible, so i don't waste clock cycles to start readout. Ideally i should be able to control how long this signal are, new pulse must start at rising edge of trigger pulse, falling edge is ignored, and new falling edge is generated automatically, when x ns had passed from rising edge ( i could do that with 555 timer, but it's is too slow, and it would be nice to use Altera Cyclone 4 EP4CE6E17C6 for that.
https://www.alteraforum.com/forum/attachment.php?attachmentid=8791 This circuit is working very well, only problem is that if trigger is very long, i will miss clock cycles to start readout, and it will be delayed as long TRIGGER is high level. That's why i need to generate falling edge as fast as i can, but at the same time that fpga could catch it
