SignalTap-II -> "instance not found" error

[Altera_Forum]

Hi all, 

I'm receiving the "instance not found" error on the SignalTap-II - attached please find the window snapshot. Actually the error occurred when I added signals for debug. I did the full compilation of the project after adding the signals, tried to remove them - nothing helps. Does anybody knows how to fix the problem?  Thank you!  

[Altera_Forum]

Is your USB blaster cable able to detect the device?

[Altera_Forum]

--- Quote Start ---  Is your USB blaster cable able to detect the device?  --- Quote End ---    Yes, it's able to detect the device and also also scan it. I also able to program it.

[Altera_Forum]

Probably some contention with the signaltap. Can you try to remove the signaltap and create a new one?

[Altera_Forum]

tried to do this several times - nothing helps

[Altera_Forum]

Are you sure you're programming the correct file? have to loaded the correct .stp file? This can occur if the .stp file you're using for signaltap doesnt match the core in the device.

[Altera_Forum]

BTW, how can I check that the the correct *.stp file was taken during compilation? Can I check this in the reports? which one of them? Should the *.stp file be included in the Files List, which appears in the Project Navigator Tab?

[Altera_Forum]

Go to assignments -> settings > SignalTap II Logic Analyzer. 

Here you need to tick the "Enable SignalTap II Logic Analyzer" and select the correct file before you compile the design.

[Altera_Forum]

I realize this is an old thread, but I'm having this same problem. I have inserted a SignalTap instance into my design, and verified that it is included in the build via "assignments -> settings -> SignalTap II Logic Analyzer". I have also viewed the fit report log file and see that there is a SignalTap instance consuming logic resources in my design. Compilation completes without error and I can scan the JTAG chain and (after triple-checking the path) load the .sof via SignalTap. After loading the FPGA, I see the same "Invalid JTAG configuration" and "Instance not found" errors as the OP. 

 I have re-inserted SignalTap logic and re-compiled multiple times, and double checked my paths multiple times. I'm at a loss for what could be going wrong.

[Altera_Forum]

In case anyone else stumbles upon this thread looking for answers, I figured out my problem. I needed to reduce the JTAG clock rate from 24 MHz to 6 MHz. I'm still unsure why I was able to program the FPGA and run the JTAG scan tests successfully at 24 MHz. I would have expected those operations to fail as well.

[Altera_Forum]

I have seen this exact issue in my own design and it stumped me for a while, but the problem turned out to be a lack of timing constraints on the JTAG clock and the design fails setup & hold within the SignalTap instances. 

All the pieces seemed to make sense when I thought about it.   The device would program just fine because the JTAG signals only connects to the hard programming logic at power on. After programming it with a badly-P&R'ed SignalTap instance, which the JTAG signals are now routed into, the JTAG data nets would be failing setup & hold inside the fabric of the SignalTap instance, and any data returning from those instances would then be metastable or just plain wrong. The returned data would take on a random form, also corrupting any JTAG control messages along with any collected data, which explains the variety of error messages you can see in the SignalTap window. I saw maybe 4 or 5 different errors if I repeatedly clicked the Run Instance button.  This also ties in with your observation that reducing the JTAG clock rate fixed the problem, as the P&R engine would find it easier to make a valid fit on a poorly constrained design if the clock speed was reduced. You may find that the exact same P&R that fails at 24MHz works fine at 6MHz (you could test this by constraining the P&R to post-fit and then changing the timing constraints to reduce the TCK clock rate in the Static Timing Analysis tool ie. TimeQuest, and see it suddenly meet S&H).   I think a basic SDC constraints file should fix the problem, assuming you don't have one already? Or maybe there are some errors in it. At least tinkering with this for me solved the problem.  First check for clocks that are failing S&H using TimeQuest (if you haven't used TQ much there are some basic tutorials around but the tool is very powerful. The following document from the Forum User 'rysc' is a great place to start, with the first chapter being a great introduction to the most important commands. http://www.alteraforum.com/alterawiki.com/uploads/3/3f/timequest_user_guide.pdf) Use the 'Report All Summaries' macro and then see if any clocks are failing Setup or Hold. The JTAG clock is called 'altera_reserved_tck' by default. Mine was failing on Setup.  A basic SDC file with the commands 'create_clock', 'derive_pll_clocks', 'derive_clock_uncertainty' and 'set_clock_groups' is probably all that is required. Use TQ to copy out all the derived pll clocks and paste them into the 'set_clock_groups' arguments. Above linked doc also describes this step.  And that fixed it for me.   Hope this helps, but I am far from an expert, so maybe I overlooked something obvious.