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SignalTap II sample clock timing violation

Altera_Forum
Honored Contributor II
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I have a system running at 250Mhz and I want to sample certain internal signals by using signaltap ii. I learnt that I should use at least 500Mhz sample clock (double the working clock freq.) in order to have correct sampling however I received a lot of timing violations after instantiating the signaltap module. Problematc paths are from signaltap module to different places in the qsys system. I then set those paths to be faulse paths but doing so only generates even more problematic paths. 

 

I wonder what is the correct/standard way to handle such problem? 

 

Thanks!
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Altera_Forum
Honored Contributor II
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SignalTap should be running on the same clock as the signals you're sampling, in which case it's fully synchronous transfers and there's no need to oversample. (I've never heard of oversampling with SignalTap when grabbing from other, asynchronous, clock domains, but imagine it could work. Still hard to read the data since it's not just what you capture, but how it aligns with other signals, which you can't fully count on...)

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

SignalTap should be running on the same clock as the signals you're sampling, in which case it's fully synchronous transfers and there's no need to oversample. (I've never heard of oversampling with SignalTap when grabbing from other, asynchronous, clock domains, but imagine it could work. Still hard to read the data since it's not just what you capture, but how it aligns with other signals, which you can't fully count on...) 

--- Quote End ---  

 

Oh..Does that mean I can use main working clock directly as the sampling clock?
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Altera_Forum
Honored Contributor II
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Yes. SignalTap is just like any other logic in your design, and could technically be created by hand. So just have it run off the same clock as your logic.

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