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Honored Contributor I
913 Views

SignalTap issue with lpm_mult dataa bits

Hi, 

 

I am using the SignalTap to read values off of my design. When I probe the inputs to the lpm_mult, dataa and datab, I come across wrong values. 

 

My inputs are both 16-bits wide. However, in the SignalTap, it shows that my inputs are 20-bits wide. The following is the signal for data in SignalTap: 

lpm_multt:inst|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_t5i:auto_generated|dataa[0..19] 

 

My Modelsim-Altera simulation results do not match the SignalTap results. 

 

Can you please help me in finding out the issue here?  

Thank you.
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5 Replies
Honored Contributor I
25 Views

Btw, I am using the Stratix IV board. So I hope it supports the lpm_mult megafunction.

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Honored Contributor I
25 Views

can you post the lpm_mult .v/.vhd variation?

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Honored Contributor I
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Here is the .vhd for the lpm_mult megafunction I am using: 

 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

 

LIBRARY lpm; 

USE lpm.all; 

 

ENTITY multlpm IS 

PORT 

clock : IN STD_LOGIC ; 

dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 

result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 

); 

END multlpm ; 

 

 

ARCHITECTURE SYN OF multlpm IS 

 

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); 

SIGNAL sub_wire1_bv : BIT_VECTOR (15 DOWNTO 0); 

SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); 

 

 

 

COMPONENT lpm_mult 

GENERIC ( 

lpm_hint : STRING; 

lpm_pipeline : NATURAL; 

lpm_representation : STRING; 

lpm_type : STRING; 

lpm_widtha : NATURAL; 

lpm_widthb : NATURAL; 

lpm_widthp : NATURAL 

); 

PORT ( 

clock : IN STD_LOGIC ; 

dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 

datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 

result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 

); 

END COMPONENT; 

 

BEGIN 

sub_wire1_bv(15 DOWNTO 0) <= "0000000001100100"; 

sub_wire1 <= To_stdlogicvector(sub_wire1_bv); 

result <= sub_wire0(31 DOWNTO 0); 

 

lpm_mult_component : lpm_mult 

GENERIC MAP ( 

lpm_hint => "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5", 

lpm_pipeline => 1, 

lpm_representation => "SIGNED", 

lpm_type => "LPM_MULT", 

lpm_widtha => 16, 

lpm_widthb => 16, 

lpm_widthp => 32 

PORT MAP ( 

clock => clock, 

dataa => dataa, 

datab => sub_wire1, 

result => sub_wire0 

); 

 

 

 

END SYN;
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Honored Contributor I
25 Views

The shown Megafunction won't expose dataa[19..0].

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Honored Contributor I
25 Views

I guess I was reading the wrong nodes in SignalTap. I found the correct input nodes that only show 16 bits. 

 

Thank you all for your help.
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