Simulating a VHDL array

Altera_Forum · ‎04-05-2011

Modelsim-Altera returns an error when I try to drive the 'x' inputs in the code below:

"Error: (vsim-3455) Can force arrays only if they are one-dimensional arrays of character enums."

Here is the listing:

library ieee;

use ieee.std_logic_1164.all;

package pkg_array is

type row is array(7 downto 0) of std_logic;

type vec_array is array(integer range <>) of row;

end pkg_array;

library ieee;

use ieee.std_logic_1164.all;

use work.pkg_array.all;

entity gen_mux is

generic (n: integer := 2); -- Set the number of 8 bit inputs

port(

x: in vec_array(0 to (2**n - 1));

sel: in integer range 0 to (2**n - 1);

y: out row);

end gen_mux;

architecture description of gen_mux is

begin

y <= x(sel);

end description;

Is there a better way to do this? Or is there a way to write this so Modelsim will allow the x arrays to be driven?

Thanks for any help,

Steve

Altera_Forum · ‎04-05-2011

You shouldnt really create your own arrays of std_logic. Thats what std_logic_vectors are for. You cause all sorts of problems when you dont use std_logic_vector.

But you havent posted your code where you drive X, so I cant see where the error is occuring.

Altera_Forum · ‎04-06-2011

Okay, thanks for the help. I changed the code to:

library ieee;

use ieee.std_logic_1164.all;

package pkg_array is

type vec_array is array(integer range <>) of std_logic_vector(7 downto 0);

end pkg_array;

library ieee;

use ieee.std_logic_1164.all;

use work.pkg_array.all;

entity gen_mux is

generic (n: integer := 2); -- Set the number of 8 bit inputs (2**n)

port(

x: in vec_array(0 to (2**n - 1));

sel: in integer range 0 to (2**n - 1);

y: out std_logic_vector(7 downto 0));

end gen_mux;

architecture description of gen_mux is

begin

y <= x(sel);

end description;

Here's the tcl command I used to drive the x inputs, with the resultant error:

force -freeze sim:/gen_mux/x {{{00000001} {00000111} {10101010} {11110000}}} 0# ** Error: (vsim-3455) Can force arrays only if they are one-dimensional arrays of character enums.

Is there a way to change this code so that Modelsim-Altera will allow me to drive the inputs?

Thanks,

Steve

Altera_Forum · ‎04-06-2011

Create a testbench rather than forcing inputs from the command line. As the error says, you can only force simple inputs.

Altera_Forum · ‎04-06-2011

Okay, here's my attempt at a testbench:


-- Test Bench for Gen_Mux
--   4-6-11
library ieee;
use ieee.std_logic_1164.all;
 
use work.pkg_array.all;
 
entity test_bench is
 generic (n: integer := 2);
end entity test_bench;
 
architecture test of test_bench is
 signal x: vec_array(0 to (2**n - 1));
 signal sel: integer range 0 to (2**n - 1);
 signal y: std_logic_vector(7 downto 0);
 
 begin
  dut: entity work.Gen_Mux(description)
   port map(
      x => x,
      sel => sel,
      y => y);
  stimulus: process is
  begin
    x(0) <= "10001001";
    x(1) <= "00001111";
    x(2) <= "11110000";
    x(3) <= "10101010";
    sel <= 2;
    wait for 5 ns;
    sel <= 0;
    wait;
  end process stimulus;
end test;

The code compiles without errors in Quartus 10.1 sp1. Does it look correct? Any suggestions?

Also, I have included this file in Assignments > Settings > EDA Tool Settings > Simulation > NativeLink Settings > Compile Test Bench..., but nothing happens when I run ModelSim-Altera. Is there another setting that I am missing somewhere?

Thanks,

Steve

Altera_Forum · ‎04-06-2011

no point in compiling it in quartus it will just synthesise everything away. you need to run it in modelsim. Looks like you got the theory right - try running it.

Altera_Forum · ‎04-06-2011

Thank you Tricky. It works perfectly. :-)