Single Pulse in output with pulse width ibility control

[Altera_Forum]

Hi everyone. I have used many ways to create single out pulse with pulse width bility. So far as I know I have to use counter to count clock pulses and make the output one and zero. 

I have used state machine to write my code but always there is an unwanted pulse before my code configuration. All suggestions are Welcomed.  the output waveform is attached.  my code:  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity ltd_auto is   port  (  clk : in std_logic;  data_out: out std_logic  &nbsp;);   end ltd_auto;   Architecture behavioral of ltd_auto is   signal c : integer:= 0; constant a : integer:= 2; constant b : integer:= 3;   type state_type is (idle, delay, zero); signal next_s: state_type;   begin   process (clk)  begin  if (rising_edge(clk))then  case next_s is  when idle =>  c <= c + 1;  next_s <= delay;  when delay =>  if (c = a) then  data_out <= '1';  end if;  if (c = b) then  data_out <= '0';  next_s <= zero;  else  c <= c + 1;  end if;  when zero =>  c <= 0;  end case;  end if;  end process; end behavioral;

[Altera_Forum]

The initial high is while the FPGA is being configured. Once configured the output is driven low and fires a single pulse as your state machine describes. 

If you want your output to be low during configuration you have to add a pull-down resistor to the FPGA's pin.

[Altera_Forum]

or just create a initial delay either by sensing a button being pressed or when a counter reaches a certain value after FPGA is configured .

[Altera_Forum]

--- Quote Start ---  The initial high is while the FPGA is being configured. Once configured the output is driven low and fires a single pulse as your state machine describes. If you want your output to be low during configuration you have to add a pull-down resistor to the FPGA's pin.  --- Quote End ---   Thanks for your time josyb. I have tried to change the pull-down resistor located in Pin planner but there wasn't any change in output. I would really appreciate if you be more specific with examples or extra information. I have heard of External pull-down resistor? any idea how it works? Regards

[Altera_Forum]

--- Quote Start ---  or just create a initial delay either by sensing a button being pressed or when a counter reaches a certain value after FPGA is configured .  --- Quote End ---   Hi dude, Can you be more described? I have tried to use reset before rising_edge (clk) and make my output '0' but it did not work also. And because of planned usage of fpga using buttons are not easy. I want to use it in a compact place beside other devices and it could be difficult for me to use buttons. still any idea with/without buttons are welcomed. Regards