SoC component

[Altera_Forum]

Hi every body, 

  please i need a confirmation before i start to create my SoC. In attached picture wich represent the component that i need in my SoC. I don't know really, in each SoC it is indispensable to use a ext flash or SSRAM.  In my application i need just a NiosII processor, and the onchip memory. For this reason i try to minimize my own SoC.

[Altera_Forum]

If your software is small enough, you can try and fit it in the on-chip RAM. But you'll me more comfortable with an external SSRAM. 

If you only use the on-chip memory, then you don't need a flash interface. The on-chip memory can be initialized during the FPGA configuration and you don't need a bootloader to load the software from a flash.

[Altera_Forum]

--- Quote Start ---  If your software is small enough, you can try and fit it in the on-chip RAM. But you'll me more comfortable with an external SSRAM. If you only use the on-chip memory, then you don't need a flash interface. The on-chip memory can be initialized during the FPGA configuration and you don't need a bootloader to load the software from a flash.  --- Quote End ---     HI Daixiwen  Thank you for your reply,  I implemented the the previous architecture. I assignement the pins and i compile the project, everything is fine. But when i try to execute a simple hello world code to make sure that all is good. It appear to me error "Problem Occurred Launching Hardware' has encountered a problem. Downloading Elf Process failed". I don't know if this error is caused by the harware or by the software.  what can i do to resolve this problem:(?  Thanks

[Altera_Forum]

Hi, 

 I resolve the problem by increase the memory size. But when the program is loaded to the FPGA, the code does not appear anything. I find that the clock have a bad assignement pin. Just when i related the frequency directly to source clock, it work. Then the problem now is i don't know how i will assigement the clock output of the PLL. the book of assignement pin http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf. In my SOPC i have a PLL that the source is related to an oscillator of 50 Mhz, wich is related to PIN_AC34.  I don't find it in the book, the assigenemnt of PLL output.  Thanks

[Altera_Forum]

I'm not sure I understand your problem, but if you have a pll in your sopc system, then its outputs will appear in the clock list and you can select it from there.

[Altera_Forum]

--- Quote Start ---  I'm not sure I understand your problem, but if you have a pll in your sopc system, then its outputs will appear in the clock list and you can select it from there.  --- Quote End ---    Hi Daixiwen,  I Know that's outputs will appear in the clock list as you say , i will re-explain, my problem is in assignement pin. I don't know exactly the assignement pin correspond to the ouput_clock of the pll.   I reltad the input of pll to PIN_AC34, that the output pll.c0 i don't know exactly to wich pinshould i connect the output.

[Altera_Forum]

It's not connected to any pin, it's inside the FPGA.

[Altera_Forum]

--- Quote Start ---  It's not connected to any pin, it's inside the FPGA.  --- Quote End ---   Ok, i know that it couldn't connect to any pin. The input should be inside the FPGA but the output is in the FPGA because it will pass with the PLL. Please this is the book that contain the assignement pin for my board STRATIX IV http://www.altera.com/literature/man..._dev_board.pdf (http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf). Can you give me the pin that i should related the output.  Thank you

[Altera_Forum]

I'm sorry but I still don't understand what your problem is or what you want to achieve. 

The PLL needs a valid clock input. It can either be the output of another pll or one of the FPGA's pins. In your case you can pick up from the kit manual the number of the pin that is connected to an oscillator, and connect that pin to the pll's input. This seems to be what you did. Now the PLL's outputs are connected to the FPGA's global clock network and can be directly used by your logic. It isn't related to any pin.

[Altera_Forum]

--- Quote Start ---  I'm sorry but I still don't understand what your problem is or what you want to achieve. The PLL needs a valid clock input. It can either be the output of another pll or one of the FPGA's pins. In your case you can pick up from the kit manual the number of the pin that is connected to an oscillator, and connect that pin to the pll's input. This seems to be what you did. Now the PLL's outputs are connected to the FPGA's global clock network and can be directly used by your logic. It isn't related to any pin.  --- Quote End ---     Ah ok, clear now, then why in the assignement pins he appear to me the output clock, can i let then the output clock without any assignement. For the input i related it with an oscillator as you say.

[Altera_Forum]

Oh okay, are you using the Sopc component directly as a top level file? In that case Sopc Builder may have created a clock output, and the pin planner wants you to place it somewhere. As you don't need it, you can simply connect it to an unused I/O (such as one of the pins on the expansion ports) or an SMA output. 

If you instantiate the Sopc component inside your top level file, you can simply leave the clock output unconnected.

[Altera_Forum]

--- Quote Start ---  Oh okay, are you using the Sopc component directly as a top level file? In that case Sopc Builder may have created a clock output, and the pin planner wants you to place it somewhere. As you don't need it, you can simply connect it to an unused I/O (such as one of the pins on the expansion ports) or an SMA output. If you instantiate the Sopc component inside your top level file, you can simply leave the clock output unconnected.  --- Quote End ---    Yes i using the SOPC builer, the problem is resolved now, i relate it directly as you say to unused i/O pin.  Thank you a lot for your helps Daixiwen :-P.