Hello Everyone,
We are using EP4SGX230KF40I3 deivces in our project. Each FPGA will process 6 LTM9010 (8-channels ADC). The ADC's sampling rate is 100M. LTM9010's output speed is limitted no more than 1Gbps, so the ADC has to run at 2-lane mode. Which means there are at least 114 LVDS pairs connected to FPGA. However, EP4SGX230KF40I3 row I/O only has 88 LVDS pairs, so some column I/O LVDS pairs must involve in receiving ADC output LVDS pairs.
The column LVDS pairs of Stratix IV GX are true LVDS without dedicated SERDES. Users have to implement SERDES in the core logic. My question is how to implement SERDES of LVDS in logic? Is there any information about it?
Thanks
