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Hello,
I have some problems about EPM570. What's the GCLK maximum value that could be accepted? I searched datasheet and found it can input higher than 100 MHz. But I input a 100 MHz XTAL and CPLD cannot output any signal. I also input 100 MHz to normal I/O pin and it can't be detected. I am wondering about the maximum frequency that can be accepted? Or there the I/O impedance should also be take into consideration? I searched internet and found most of people use 50 MHz to GCLK, I dont know why. Is there any other reference files I missed? Thanks jackleeLink Copied
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You can trust in the datasheet specifications. Obviously you did something wrong, either with your hardware or software design.
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Hello,
But if I input a 80 MHz XTAL and CPLD can output the correct signal. And the I/O pin is also can be detected,. I don't know why 80 MHz can be detected but 100 MHz can't. Thanks jacklee- Mark as New
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It kinda depends on what you're doing... It sounds like your design works at 80mhz but not at 100mhz. Have you tried doing a timing analysis?
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Don't know what you mean with "detect I/O pin"?
Besides correct waveform of the clock oscillator signal (voltage level, rise/fall times, clean edges), timing analysis should verify that the design can run at 100 MHz.- Mark as New
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You're looking at your clock setup time. Your tco ( clock-to-output ) worst case shows 12.908ns or a maximum of 77.47133560582584mhz, so you're even pushing it with an 80mhz clock signal...
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The actually implemented 2-bit counter has no problems to run at several 100 MHz. So there's apparently a hardware problem with the clock input or something similar. Nothing that could be seen from the given information, unfortunately.
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Two silly questions to make sure first.
1. Could you measure 100MHz from input pin? Maybe your scope cannot "see" that sample. 2. Is the 100MHz crystal works well? Check voltage level related.- Subscribe to RSS Feed
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