Some problems about altera_pll on cyclone V device

[Altera_Forum]

Hello everyone, 

 I just met a problem about altera_pll on my cyclone V board. There is a 5CEFA4F23C8 FPGA on my board and the FPGA is conneted to a crystal oscillator via a clock input pin.   The crystal frequency is 50MHz and i want to generate an 100MHz signal but the output is nothing(zero).   I tested the reset signal and the crystal and found the reset is logic high(3.3V) and the crystal is 50MHz sine wave. Further more, I also tested the "locked" signal of the altera_pll and found it low.  Is there anyone who has met similar problem and can give me some advice?  Thanks a lot. Regards.  Alex

[Altera_Forum]

did you check RREF_TL on your board? 

 from pin Connection Guide: reference pins  RREF_TL Input - Reference resistor for transceiver and PLL  If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

[Altera_Forum]

--- Quote Start ---  did you check RREF_TL on your board?  from pin Connection Guide: reference pins  RREF_TL Input - Reference resistor for transceiver and PLL  If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.  --- Quote End ---    Also, make sure that the PLL settings and pin mappings are correct. I hate to state the obvious, but it is possible that the wrong input pin is selected for the PLL input clock or the PLL is set for a different input clock frequency.

[Altera_Forum]

Thank you for your advice, derim。 

I just confirmed the input pins and found it correctly connected to the dedicated CLK3_P pin , so as my teammates. If I use the external clock directly, the clock is OK. But if only the altera_pll exists, the system fails.

[Altera_Forum]

--- Quote Start ---  Thank you for your advice, derim。 I just confirmed the input pins and found it correctly connected to the dedicated CLK3_P pin , so as my teammates. If I use the external clock directly, the clock is OK. But if only the altera_pll exists, the system fails.  --- Quote End ---    Additional obvious check: is the reset pin pulled low? The PLL expects an active-high reset, not active low. In addition, is the PLL set to auto-lock in the settings?

[Altera_Forum]

Thank you and finally found the RREF_TL pin is unconnected. I think it may be the real reason. 

    --- Quote Start ---  did you check RREF_TL on your board?  from pin Connection Guide: reference pins  RREF_TL Input - Reference resistor for transceiver and PLL  If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.  --- Quote End ---  

[Altera_Forum]

I faced the same problem and the PLL was not locking. The RREF_TL was left floating. The issue was partially solved after fixing this floating pin.

[Altera_Forum]

--- Quote Start ---  I faced the same problem and the PLL was not locking. The RREF_TL was left floating. The issue was partially solved after fixing this floating pin.  --- Quote End ---    Thank you for your advice, Sherif. Does your PLL work now?  You mentioned that your issur has been partially solved. I wonder what issue has not been solved now.

[Altera_Forum]

Thank you for your advice, Sherif. Does your PLL work now? 

 You mentioned that your issur has been partially solved. I wonder what issue has not been solved now.

[Altera_Forum]

The PLL issue was solved and it was working as expected. 

The chip was new to me and it is a custom board not an evaluation one. So I had a lot of things to test. But anyway, everything is good for me now. That RREF_TL caused me some hard time.