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Hi
following Altera/Intel course of about the source synchronous constraints https://learning.intel.com/Developer/learn/course/168/play/1632:223/constraining-source-synchronous-interfaces
I become confused - regarding Edge Aligned input constraints .
the definitions of Edge Align {at slides 6 and 13 (Section 2.2 and 3.5) }
is that the data is transmitted at same edge, and the instruction is to insert PLL with 180 phase shift . (slide 11 (section 3.3) and slide 13 (section 3.5) )
But the confusion is once we want to define the "input max delay" and "input min delay" at Slide 19 (3.11)
--> in the diagram here (and also the calculation ) Latch Clock is not phase shifted as expected (since we added PLL )
so my question is :
if the data is transmitted Edge-Aligned and in the Input FPGA I insert PLL which shifts the clock by 180 deg. do I need to use the equations of:
"Edge Align " , input max delay = -setup , input min delay = hold -period
or
"Center Aligned" , input max delay = period / 2 -setup , input min delay = hold - period/2
Thanks
Or
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You use the edge-aligned equations. The phase shift from the PLL happens inside the FPGA, not at the inputs, where the data and clock are still edge aligned. Use -setup and hold-period as shown.
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You use the edge-aligned equations. The phase shift from the PLL happens inside the FPGA, not at the inputs, where the data and clock are still edge aligned. Use -setup and hold-period as shown.
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