Sources for using USB 2.0 OTG Controller

[Altera_Forum]

In usb 2.0 slave hwlib (http://www.alteraforum.com/forum/showthread.php?t=45542)  

detewef (http://www.alteraforum.com/forum/member.php?u=92663) ask a possibility in HWLIB to use embedded USB controller in HPS. May be very usable to use my CV-device as flash-trinket, with keep there application codes in many variants, results of work, ...and with easy exchanges with PC, not through slow JTAG! In "Cyclone V Device Handbook" described 2 instances of OTG (On The Go, bidirectional USB) 2.0 for HPS, each may be device or host independently. Host realisation ask big efforts, Linux etc... And if suddently exist ready codes for slave drive with filesystem ? I connect OTG-output on kit to PC (Win7) through micro-USB-cable from kit set and not see new devices with Linux boot, although many "USB" mentions in console: "USB Mass Storage driver", "DWC OTG Controller", "irq 160", "USB HID core driver" etc... And if I start gpio example (http://www.altera.com/support/examples/soc/soc.html), then Win 7 has found new "Unknown Device" on USB bus: side by side with usual "FT232R USB UART" and "USB-Blaster II" :) May anybody give link to good and easy coltroller code for flash FAT32-device or like ?

[Altera_Forum]

I found 2 realisation of flash-device for microcontrollers and need use open Linux drivers (dwc_otg) in Baremetal mode, and can't read/write USB-core registers: only 0s. 

Someone can explain me a method set USB-OTG-controller# 0 in working state (ON) in Baremetal application ? Controller# 1 is greater normal :) I remove reset from USB0 (clearing bit 2 in Reset Manager register 0xFFD05014), view in Memory a region 0xFFB00000 (USB0 OTG controller registers) and see only 0s (picture "usb0") ! However, if I make this for USB1 (bit 3 in Reset Manager, region 0xFFB40000, USB1 OTG controller registers), a picture "usb1' displays many non-0 values: 0x80000000 on 0xFFB40010 (grstctl) with "indicates that the AHB Master State Machine is in the IDLE condition" after reset, 0x12345678 on 0xFFB4003C (guid) with "Reset Value 0x12345678", 0x4F54293A in 0xFFB40040 (gsnpsid) "Release number of the otg core being used is currently OTG 2.93a", and more non-0s. Using a technique of Cold-Warm-Resets (see http://www.alteraforum.com/forum/showthread.php?t=45877&p=189952#post189952) and debug from start address 0 with change reset bits in 0xFFD05014 from Memory window from 0x3FFFFFFF to 0x3FFFFFFB or 0x3FFFFFF7, I clarify that visibility of USB1-registers depends only from bit 3 of Reset Manager register 0xFFD05014, and USB0 besides bit 2 demand something more tuning. Clock not present, anymore other problems is with USB0 ? In Linux this port work successful in Host mode. If I set bit 3 in 0xFFD05014 back to 1, all non-0s in region 0xFFB40000 for USB1 turn into 0, reset is work!