I have a system where a Xilinx Zynq is driving an Arria 10 board 10Gbps, then this Arria 10 board drives 4* the same boards, also at 10Gbps.
I need to be able to transfer variable length (< 1K bytes probably) packets between devices in the system with a 'start of packet' and 'end of packet' indicator.
I do not need to combine multiple lanes for more bandwidth, each 'link' is a single Rx/Tx pair, point to point.
Ideally whatever mechanism chosen would use the trasnceiver CRC generators and checkers so that we do not need to implement this in logic. It would also be good to have as small a 'footprint' as possible.
I have > 20 years FPGA design experience, but not much with transcievers/ protocols.
Is there a 'go to' standard protocol for inter FPGA comms that is supported by Intel and Xilinx?
Thanks for any Feedback.
Sorry for the delay. I might have overlooked the email notification on this. As I understand it, your inquiries seems trending towards design implementation related inquiries. Since I am not really a design specialist, I could not really comment on which specific protocol to use in your particular case. However, for 10G, probably you could try to look into Ethernet to see if meet your requirement.
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
I am sorry, I checked back a few times after my initial post but didn't see any replies.
I also didn't get any notificiation that someone had replied.
For general reference there _doesn't_ seem to be a universally supported lightweight standard for transceiver based inter FPGA comms.
Xilinx have Aurora, Intel Superlite/ Ultralite but nothing supported by "both sides".