State of Unused I/O pins and design of isolation filter for Cyclone IV FPGA

[Altera_Forum]

Hello there, 

 Reference: Cyclone 4 EP4CE10 FPGA  I m developing a prototype board with minimum peripheral say 4 slide switches, and 4 LEDs, with a 40pin GPIO, with program persistance through Flash programming . The GPIO pins are used to interface the FPGA to CMOS(3.3V) compatile microcontrollers and devices.In the pin mapping sheet it is said, and i quote "When these IO pins are not used, they can be tied to GND".   This is regarding unused I/O pins. Since i m using the GPIO pins which are connected to 40 pins in the FPGA(I/O pins ofcourse), these GPIOs may or may not be used at any point in the usage of the board. So does it make a difference if it is kept floating when no external interfacing is done using the board, and whenever the user demands external interfacing, and this GPIOs are driven   Secondly, from the Pin Mapping Guidelines, it is mentioned to use an isolation filter to between two supplies of same value(say VCCINT and VCCD_PLL uses same 1.2V) then they are driving the voltage from the same regulator but using the said isolation filters. I dont know how to design one such filter,Any suggestion would be of great help. I m not able to attach the snap of the power supply diagram, but its from 9th page in the "Cyclone IV Device Family Pin Connection Guidelines"   Thanks in advance

[Altera_Forum]

For your GPIO pins you can leave them floating if you have pull-ups or pull-downs. Without them the pin voltage could oscillate and increase the chip consumption. You can either put some pull-us/downs on the board or use the assignment editor or pin planner to enable the internal pull-ups in the FPGA on those pins. 

As for the filter between two supplies of the same value, we usually put a ferrite. If you have enough decoupling on both FPGA supplies it should be enough. As an example you can download one of the FPGA development kit support files and have a look at the schematics.

[Altera_Forum]

Dear Daixiwen, 

 How to ensure the enough decoupling is present on each FPGA supply ? What is the suggested values of decoupling capacitors on each VCCINT & VCCD_PLL (@1.2V)supplies & Similarly on each VCCA & VCCA_PLL(@2.5v).  I am not using any PLLs inside FPGA. I am using maximum FPGA I/O signal frequency is @150MHz.  Please guide me how to calculate decoupling on these FPGA power pins. I am using cyclone - IV E FPGA.  Regards, Thulasi

[Altera_Forum]

For the 2nd question. you can use ferrite bead BLM21PG331SN1 and 10uF for isolation filter. You can refer the altera pcie kit schematic for more info.

[Altera_Forum]

The amount of decoupling is very design dependent. You can use the power distribution network (http://www.altera.com/technology/signal/power-distribution-network/sgl-pdn.html) tool to find an optimal distribution. Alternatively if you find a development kit that uses the same FPGA than you, you can copy the decoupling distribution from the kit's schematics, there is a good chance it will work with your design too, just maybe overkill.

[Altera_Forum]

Dear sir, 

 Q1. I used PDN for VCCINT power supply. PDN tool suggested 22nF(1No.) & 1uF(1No.) capacitors. Please clarify, the suggested capacitors by PDN tool are for a single VCCINT power pin or for all VCCINT power pins of FPGA. In my FPGA there are 28 VCCINT pins.   Q2. I am not going to use any PLLs inside FPGA. Do I still need to use Ferrite bead between VCCINT & VCCD_PLL or if I put the suggested decoupling capacitors by PDN tool for each VCCINT & VCCD_PLL is enough.  Q3. Similarly, for VCCA pins, as I am not using any PLLs inside FPGA, do I still need to use Ferrite bead between Linear regulator output & VCCA or the suggested decoupling capacitors by PDN tool is enough for each VCCA pin  Please clarify.  Regards, Thulasi

[Altera_Forum]

The suggested capacitors is for the whole power plane, not per pin. It doesn't seem to be a lot, are you sure you put the right current requirements in the sheet? 

As for the plls supplies they are also use for other things, such as the configuration and JTAG internal logic. But I guess that it won't be that critical. I think you can avoid using ferrite, but you'll never get a guarantee that such a setting is safe. Besides, later in the project you could decide that you need a pll for an extra clock frequency that you didn't think about. Ferrites are rather small, so at least having the 0603 or 0402 footprint just in case you need the ferrite later would be safer IMHO.