Statemachine error

[Altera_Forum]

Hi I think i have a statemachine that makes a ibutton interface top communicating.  

I think it is in the code below. Could some one have a look. On thing I found that DQ_IN is in input that is not clocked but is used for state selection.  I guess this could put the statemachine in an unconditioned state (metainstability) But i'm having a hard time proving this.  I can't find it in practice nor any documentation about this.  This is the code:   OneWireReset_machine: process(clk, MR)  -- machine variables  variable count: INTEGER range 0 to 1000;  variable smCnt: INTEGER range 0 to 32;   begin  if (MR = '1') then --synchronous reset  count:=0;  OneWireReset <= Idle;  pdr <= '1';   elsif (clk'event and clk = '1') then  if (clk_en = '1') then  case OneWireReset is   when Idle =>  count := 0;  if owr = '0' then  OneWireReset <= Idle;  elsif owr = '1' then  OneWireReset <= Reset_Low;  end if;   when Reset_Low =>  count := count +1;  pdr <= '1';  if count = 500 then  OneWireReset <= PD_Wait;  end if;   when PD_Wait =>   count := count +1;   if count = 515 then   OneWireReset <= PD_Edge;   end if;     when PD_Edge =>  count := count +1;  if DQ_in = '0' then -- Adapted for Granada situation  OneWireReset <= PD_Sample;  smCnt := 0;  elsif count = 560 then  OneWireReset <= PD_Sample;  smCnt := 0;  end if;   when PD_Sample =>  count := count +1;  smCnt := smCnt +1;  if smCnt = 30 then  pdr <= DQ_in; -- presence detect register  OneWireReset <= Reset_High;  end if;   when Reset_High =>  count := count +1;  if count = 1000 then  OneWireReset <= Reset_End;  end if;   when Reset_End =>  OneWireReset <= Idle;   when others =>  null;   end case;  end if;  end if;  end process;

[Altera_Forum]

simple check - synchronise DQ_in.

[Altera_Forum]

Hi Thanx for the answer. That is what I did but I need solid proof that that was the issue.  

 The error in the machine can't be introduced on command and happens random. Sometimes once each day and on other machines once in a week.

[Altera_Forum]

unsynchronise it - if the problem comes back, thats your problem. You only made a small change. 

Using unsynchronised signals in synchronised logic has a habit of causing these problems.